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Match ar/ar.c

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This commit is contained in:
dbalatoni13 2024-12-30 20:54:58 +01:00
parent 619179bb2d
commit dd04a5faff
2 changed files with 277 additions and 143 deletions
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2
configure.py
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@ -567,7 +567,7 @@ config.libs = [
DolphinLib(
"ar",
[
Object(NonMatching, "dolphin/ar/ar.c"),
Object(MatchingFor("GMPE01_00", "GMPE01_01"), "dolphin/ar/ar.c"),
Object(MatchingFor("GMPE01_00", "GMPE01_01"), "dolphin/ar/arq.c"),
],
),

180
src/dolphin/ar/ar.c
View file

@ -2,6 +2,7 @@
#include "dolphin/hw_regs.h"
#include "dolphin/os.h"
#include "dolphin/os/OSCache.h"
static ARCallback __AR_Callback;
static u32 __AR_Size;
@ -18,7 +19,10 @@ static void __ARHandler(__OSInterrupt interrupt, OSContext* context);
static void __ARChecksize(void);
static void __ARClearArea(u32 start_addr, u32 length);
ARCallback ARRegisterDMACallback(ARCallback callback) {
// TODO import defines for magic numbers from other repos
ARCallback ARRegisterDMACallback(ARCallback callback)
{
ARCallback oldCb;
BOOL enabled;
oldCb = __AR_Callback;
@ -28,7 +32,8 @@ ARCallback ARRegisterDMACallback(ARCallback callback) {
return oldCb;
}
u32 ARGetDMAStatus() {
u32 ARGetDMAStatus()
{
BOOL enabled;
u32 val;
enabled = OSDisableInterrupts();
@ -37,7 +42,8 @@ u32 ARGetDMAStatus() {
return val;
}
void ARStartDMA(u32 type, u32 mainmem_addr, u32 aram_addr, u32 length) {
void ARStartDMA(u32 type, u32 mainmem_addr, u32 aram_addr, u32 length)
{
BOOL enabled;
enabled = OSDisableInterrupts();
@ -52,7 +58,8 @@ void ARStartDMA(u32 type, u32 mainmem_addr, u32 aram_addr, u32 length) {
OSRestoreInterrupts(enabled);
}
u32 ARAlloc(u32 length) {
u32 ARAlloc(u32 length)
{
u32 tmp;
BOOL enabled;
@ -68,7 +75,8 @@ u32 ARAlloc(u32 length) {
}
#if NONMATCHING
u32 ARFree(u32* length) {
u32 ARFree(u32 *length)
{
BOOL old;
old = OSDisableInterrupts();
@ -129,9 +137,13 @@ lbl_8036DAB4:
/* clang-format on */
#endif
BOOL ARCheckInit() { return __AR_init_flag; }
BOOL ARCheckInit()
{
return __AR_init_flag;
}
u32 ARInit(u32* stack_index_addr, u32 num_entries) {
u32 ARInit(u32 *stack_index_addr, u32 num_entries)
{
BOOL old;
u16 refresh;
@ -164,16 +176,20 @@ u32 ARInit(u32* stack_index_addr, u32 num_entries) {
return __AR_StackPointer;
}
u32 ARGetBaseAddress(void) { return 0x4000; }
void ARSetSize(void) { }
void ARSetSize(void)
u32 ARGetBaseAddress(void)
{
return 0x4000;
}
u32 ARGetSize() { return __AR_Size; }
u32 ARGetSize()
{
return __AR_Size;
}
static void __ARHandler(__OSInterrupt interrupt, OSContext* context) {
static void __ARHandler(__OSInterrupt interrupt, OSContext *context)
{
OSContext exceptionContext;
u16 tmp;
@ -195,22 +211,27 @@ static void __ARHandler(__OSInterrupt interrupt, OSContext* context) {
#define RoundUP32(x) (((u32)(x) + 32 - 1) & ~(32 - 1))
void __ARClearInterrupt(void) {
void __ARClearInterrupt(void)
{
u16 tmp;
tmp = __DSPRegs[5];
tmp = (u16)((tmp & ~(0x00000080 | 0x00000008)) | 0x00000020);
__DSPRegs[5] = tmp;
}
u16 __ARGetInterruptStatus(void) { return ((u16)(__DSPRegs[5] & 0x0200)); }
static void __ARWaitForDMA(void) {
while (__DSPRegs[5] & 0x0200) {
}
u16 __ARGetInterruptStatus(void)
{
return ((u16)(__DSPRegs[5] & 0x0200));
}
static void __ARWriteDMA(u32 mmem_addr, u32 aram_addr, u32 length) {
static void __ARWaitForDMA(void)
{
while (__DSPRegs[5] & 0x0200) { }
}
static void __ARWriteDMA(u32 mmem_addr, u32 aram_addr, u32 length)
{
__DSPRegs[16] = (u16)((__DSPRegs[16] & ~0x03ff) | (u16)(mmem_addr >> 16));
__DSPRegs[16 + 1] = (u16)((__DSPRegs[16 + 1] & ~0xffe0) | (u16)(mmem_addr & 0xffff));
@ -228,7 +249,8 @@ static void __ARWriteDMA(u32 mmem_addr, u32 aram_addr, u32 length) {
__ARClearInterrupt();
}
static void __ARReadDMA(u32 mmem_addr, u32 aram_addr, u32 length) {
static void __ARReadDMA(u32 mmem_addr, u32 aram_addr, u32 length)
{
__DSPRegs[16] = (u16)((__DSPRegs[16] & ~0x03ff) | (u16)(mmem_addr >> 16));
__DSPRegs[16 + 1] = (u16)((__DSPRegs[16 + 1] & ~0xffe0) | (u16)(mmem_addr & 0xffff));
@ -246,6 +268,118 @@ static void __ARReadDMA(u32 mmem_addr, u32 aram_addr, u32 length) {
__ARClearInterrupt();
}
static void __ARChecksize(void) {
//TODO: Implement for this SDK version
void __ARChecksize(void)
{
u8 test_data_pad[0x20 + 31];
u8 dummy_data_pad[0x20 + 31];
u8 buffer_pad[0x20 + 31];
u32 *test_data;
u32 *dummy_data;
u32 *buffer;
u16 ARAM_mode;
u32 ARAM_size;
u32 i;
while (!(__DSPRegs[11] & 1))
;
ARAM_mode = 3;
ARAM_size = __AR_InternalSize = 0x1000000;
__DSPRegs[9] = (u16)((__DSPRegs[9] & ~(0x00000007 | 0x00000038)) | 0x20 | 2 | 1);
test_data = (u32 *)(RoundUP32((u32)(test_data_pad)));
dummy_data = (u32 *)(RoundUP32((u32)(dummy_data_pad)));
buffer = (u32 *)(RoundUP32((u32)(buffer_pad)));
for (i = 0; i < 8; i++) {
*(test_data + i) = 0xdeadbeef;
*(dummy_data + i) = 0xbad0bad0;
}
DCFlushRange((void *)test_data, 0x20);
DCFlushRange((void *)dummy_data, 0x20);
__AR_ExpansionSize = 0;
__ARWriteDMA((u32)dummy_data, ARAM_size, 0x20U);
__ARWriteDMA((u32)dummy_data, ARAM_size + 0x200000, 0x20U);
__ARWriteDMA((u32)dummy_data, ARAM_size + 0x01000000, 0x20U);
__ARWriteDMA((u32)dummy_data, ARAM_size + 0x200, 0x20U);
__ARWriteDMA((u32)dummy_data, ARAM_size + 0x400000, 0x20U);
memset((void *)buffer, 0, 0x20);
DCFlushRange((void *)buffer, 0x20);
__ARWriteDMA((u32)test_data, ARAM_size + 0x0000000, 0x20);
DCInvalidateRange((void *)buffer, 0x20);
__ARReadDMA((u32)buffer, ARAM_size + 0x0000000, 0x20);
PPCSync();
if (buffer[0] == test_data[0]) {
memset((void *)buffer, 0, 0x20);
DCFlushRange((void *)buffer, 0x20);
__ARReadDMA((u32)buffer, ARAM_size + 0x0200000, 0x20);
PPCSync();
if (buffer[0] == test_data[0]) {
ARAM_mode |= 0 << 1;
ARAM_size += 0x0200000;
__AR_ExpansionSize = 0x0200000;
}
else {
memset((void *)buffer, 0, 0x20);
DCFlushRange((void *)buffer, 0x20);
__ARReadDMA((u32)buffer, ARAM_size + 0x1000000, 0x20);
PPCSync();
if (buffer[0] == test_data[0]) {
ARAM_mode |= 4 << 1;
ARAM_size += 0x0400000;
__AR_ExpansionSize = 0x0400000;
}
else {
memset((void *)buffer, 0, 0x20);
DCFlushRange((void *)buffer, 0x20);
__ARReadDMA((u32)buffer, ARAM_size + 0x0000200, 0x20);
PPCSync();
if (buffer[0] == test_data[0]) {
ARAM_mode |= 8 << 1;
ARAM_size += 0x800000;
__AR_ExpansionSize = 0x0800000;
}
else {
memset((void *)buffer, 0, 0x20);
DCFlushRange((void *)buffer, 0x20);
__ARReadDMA((u32)buffer, ARAM_size + 0x0400000, 0x20);
PPCSync();
if (buffer[0] == test_data[0]) {
ARAM_mode |= 12 << 1;
ARAM_size += 0x1000000;
__AR_ExpansionSize = 0x1000000;
}
else {
ARAM_mode |= 16 << 1;
ARAM_size += 0x2000000;
__AR_ExpansionSize = 0x2000000;
}
}
}
}
__DSPRegs[9] = (u16)((__DSPRegs[9] & ~(0x07 | 0x38)) | ARAM_mode);
}
*(u32 *)OSPhysicalToUncached(0x00D0) = ARAM_size;
__AR_Size = ARAM_size;
}