1201 lines
32 KiB
C
1201 lines
32 KiB
C
#include "TRK_MINNOW_DOLPHIN/ppc/Generic/targimpl.h"
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#include "TRK_MINNOW_DOLPHIN/Os/dolphin/dolphin_trk.h"
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#include "TRK_MINNOW_DOLPHIN/ppc/Generic/flush_cache.h"
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#include "TRK_MINNOW_DOLPHIN/ppc/Generic/mpc_7xx_603e.h"
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#include "TRK_MINNOW_DOLPHIN/MetroTRK/Portable/msgbuf.h"
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#include "TRK_MINNOW_DOLPHIN/MetroTRK/Portable/support.h"
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#include "TRK_MINNOW_DOLPHIN/MetroTRK/Portable/notify.h"
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#include "stddef.h"
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#include "string.h"
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typedef struct memRange {
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u8* start;
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u8* end;
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BOOL readable;
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BOOL writeable;
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} memRange;
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const memRange gTRKMemMap[1] = { { (u8*)0, (u8*)-1, TRUE, TRUE } };
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typedef struct StopInfo_PPC {
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u32 PC;
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u32 PCInstruction;
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u16 exceptionID;
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} StopInfo_PPC;
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typedef struct TRKExceptionStatus {
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StopInfo_PPC exceptionInfo;
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u8 inTRK;
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u8 exceptionDetected;
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} TRKExceptionStatus;
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typedef struct TRKStepStatus {
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BOOL active; // 0x0
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DSMessageStepOptions type; // 0x4
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u32 count; // 0x8
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u32 rangeStart; // 0xC
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u32 rangeEnd; // 0x10
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} TRKStepStatus;
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ProcessorRestoreFlags_PPC gTRKRestoreFlags = { FALSE, FALSE };
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static TRKExceptionStatus gTRKExceptionStatus = { { 0, 0, 0 }, TRUE, 0 };
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static TRKStepStatus gTRKStepStatus = { FALSE, DSSTEP_IntoCount, 0, 0 };
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static u16 TRK_saved_exceptionID = 0;
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ProcessorState_PPC gTRKCPUState;
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TRKState gTRKState;
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typedef unsigned char u128[16];
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u128 TRKvalue128_temp;
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Default_PPC gTRKSaveState;
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// Instruction macros
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#define INSTR_NOP 0x60000000
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#define INSTR_BLR 0x4E800020
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#define INSTR_PSQ_ST(psr, offset, rDest, w, gqr) \
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(0xF0000000 | (psr << 21) | (rDest << 16) | (w << 15) | (gqr << 12) \
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| offset)
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#define INSTR_PSQ_L(psr, offset, rSrc, w, gqr) \
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(0xE0000000 | (psr << 21) | (rSrc << 16) | (w << 15) | (gqr << 12) | offset)
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#define INSTR_STW(rSrc, offset, rDest) \
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(0x90000000 | (rSrc << 21) | (rDest << 16) | offset)
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#define INSTR_LWZ(rDest, offset, rSrc) \
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(0x80000000 | (rDest << 21) | (rSrc << 16) | offset)
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#define INSTR_STFD(fprSrc, offset, rDest) \
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(0xD8000000 | (fprSrc << 21) | (rDest << 16) | offset)
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#define INSTR_LFD(fprDest, offset, rSrc) \
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(0xC8000000 | (fprDest << 21) | (rSrc << 16) | offset)
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#define INSTR_MFSPR(rDest, spr) \
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(0x7C000000 | (rDest << 21) | ((spr & 0xFE0) << 6) | ((spr & 0x1F) << 16) \
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| 0x2A6)
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#define INSTR_MTSPR(spr, rSrc) \
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(0x7C000000 | (rSrc << 21) | ((spr & 0xFE0) << 6) | ((spr & 0x1F) << 16) \
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| 0x3A6)
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#define DSFetch_u32(_p_) (*((u32*)_p_))
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#define DSFetch_u64(_p_) (*((u64*)_p_))
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DSError TRKPPCAccessSPR(void* value, u32 spr_register_num, BOOL read);
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DSError TRKPPCAccessPairedSingleRegister(void* srcDestPtr, u32 psr, BOOL read);
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DSError TRKPPCAccessFPRegister(void* srcDestPtr, u32 fpr, BOOL read);
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DSError TRKPPCAccessSpecialReg(void* value, u32* access_func, BOOL read);
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static void TRKExceptionHandler(u16);
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void TRKInterruptHandlerEnableInterrupts(void);
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void WriteFPSCR(register f64*);
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void ReadFPSCR(register f64*);
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void __TRK_set_MSR(u32 msr);
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u32 __TRK_get_MSR();
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static void TRK_ppc_memcpy(register void* dest, register const void* src,
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register int n, register u32 param_4,
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register u32 param_5);
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void TRKRestoreExtended1Block();
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void TRKUARTInterruptHandler();
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static BOOL TRKTargetCheckStep();
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asm u32 __TRK_get_MSR()
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{
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#ifdef __MWERKS__ // clang-format off
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nofralloc
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mfmsr r3
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blr
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#endif // clang-format on
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}
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asm void __TRK_set_MSR(register u32 msr) {
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#ifdef __MWERKS__ // clang-format off
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nofralloc
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mtmsr msr
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blr
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#endif // clang-format on
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}
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#pragma dont_inline on
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DSError TRKValidMemory32(const void* addr, size_t length,
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ValidMemoryOptions readWriteable)
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{
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DSError err = DS_InvalidMemory; /* assume range is invalid */
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const u8* start;
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const u8* end;
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s32 i;
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/*
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** Get start and end addresses for the memory range and
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** verify that they are reasonable.
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*/
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start = (const u8*)addr;
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end = ((const u8*)addr + (length - 1));
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if (end < start)
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return DS_InvalidMemory;
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/*
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** Iterate through the gTRKMemMap array to determine if the requested
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** range falls within the valid ranges in the map.
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*/
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for (i = 0; (i < (s32)(sizeof(gTRKMemMap) / sizeof(memRange))); i++) {
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/*
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** If the requested range is not completely above
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** the valid range AND it is not completely below
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** the valid range then it must overlap somewhere.
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** If the requested range overlaps with one of the
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** valid ranges, do some additional checking.
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**
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*/
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if ((start <= (const u8*)gTRKMemMap[i].end)
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&& (end >= (const u8*)gTRKMemMap[i].start)) {
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/*
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** First, verify that the read/write attributes are
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** acceptable. If so, then recursively check any
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** part of the requested range that falls before or
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** after the valid range.
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*/
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if (((readWriteable == VALIDMEM_Readable)
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&& !gTRKMemMap[i].readable)
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|| ((readWriteable == VALIDMEM_Writeable)
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&& !gTRKMemMap[i].writeable)) {
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err = DS_InvalidMemory;
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} else {
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err = DS_NoError;
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/*
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** If a portion of the requested range falls before
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** the current valid range, then recursively
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** check it.
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*/
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if (start < (const u8*)gTRKMemMap[i].start)
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err = TRKValidMemory32(
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start, (u32)((const u8*)gTRKMemMap[i].start - start),
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readWriteable);
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/*
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** If a portion of the requested range falls after
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** the current valid range, then recursively
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** check it.
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** Note: Only do this step if the previous check
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** did not detect invalid access.
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*/
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if ((err == DS_NoError) && (end > (const u8*)gTRKMemMap[i].end))
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err = TRKValidMemory32(
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(const u8*)gTRKMemMap[i].end,
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(u32)(end - (const u8*)gTRKMemMap[i].end),
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readWriteable);
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}
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break;
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}
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}
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return err;
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}
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#pragma dont_inline reset
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static asm void TRK_ppc_memcpy(register void* dest, register const void* src,
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register int n, register u32 param_4,
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register u32 param_5) {
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#ifdef __MWERKS__ // clang-format off
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#define msr r8
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#define byte r9
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#define count r10
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nofralloc
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mfmsr msr
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li count, 0
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top_loop:
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cmpw count, n
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beq out_loop
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mtmsr param_5
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sync
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lbzx byte, count, src
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mtmsr param_4
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sync
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stbx byte, count, dest
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addi count, count, 1
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b top_loop
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out_loop:
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mtmsr msr
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sync
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blr
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#undef count
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#undef byte
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#undef msr
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#endif // clang-format on
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}
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#pragma dont_inline on
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DSError TRKTargetAccessMemory(void* data, u32 start, size_t* length,
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MemoryAccessOptions accessOptions, BOOL read)
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{
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DSError error;
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u32 target_msr;
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void* addr;
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u32 trk_msr;
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TRKExceptionStatus tempExceptionStatus = gTRKExceptionStatus;
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gTRKExceptionStatus.exceptionDetected = FALSE;
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addr = (void*)TRKTargetTranslate(start);
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error = TRKValidMemory32(addr, *length,
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read ? VALIDMEM_Readable : VALIDMEM_Writeable);
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if (error != DS_NoError) {
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*length = 0;
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} else {
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target_msr = __TRK_get_MSR();
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trk_msr = target_msr | gTRKCPUState.Extended1.MSR & 0x10;
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if (read) {
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TRK_ppc_memcpy(data, addr, *length, target_msr, trk_msr);
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} else {
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TRK_ppc_memcpy(addr, data, *length, trk_msr, target_msr);
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TRK_flush_cache(addr, *length);
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if ((void*)start != addr) {
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TRK_flush_cache((void*)start, *length);
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}
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}
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}
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if (gTRKExceptionStatus.exceptionDetected) {
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*length = 0;
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error = DS_CWDSException;
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}
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gTRKExceptionStatus = tempExceptionStatus;
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return error;
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}
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#pragma dont_inline reset
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DSError TRKTargetReadInstruction(void* data, u32 start)
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{
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DSError error;
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size_t registersLength = 4;
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error = TRKTargetAccessMemory(data, start, ®istersLength,
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MEMACCESS_UserMemory, TRUE);
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if (error == DS_NoError && registersLength != 4) {
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error = DS_InvalidMemory;
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}
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return error;
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}
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DSError TRKTargetAccessDefault(u32 firstRegister, u32 lastRegister,
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TRKBuffer* b, size_t* registersLengthPtr,
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BOOL read)
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{
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DSError error;
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u32 count;
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u32* data;
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TRKExceptionStatus tempExceptionStatus;
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if (lastRegister > 0x24) {
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return DS_InvalidRegister;
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}
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tempExceptionStatus = gTRKExceptionStatus;
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gTRKExceptionStatus.exceptionDetected = FALSE;
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data = gTRKCPUState.Default.GPR + firstRegister;
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count = (lastRegister - firstRegister) + 1;
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*registersLengthPtr = count * sizeof(u32);
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if (read) {
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error = TRKAppendBuffer_ui32(b, data, count);
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} else {
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error = TRKReadBuffer_ui32(b, data, count);
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}
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if (gTRKExceptionStatus.exceptionDetected) {
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*registersLengthPtr = 0;
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error = DS_CWDSException;
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}
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gTRKExceptionStatus = tempExceptionStatus;
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return error;
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}
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DSError TRKTargetAccessFP(u32 firstRegister, u32 lastRegister, TRKBuffer* b,
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size_t* registersLengthPtr, BOOL read)
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{
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u64 temp;
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DSError error;
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TRKExceptionStatus tempExceptionStatus;
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u32 current;
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if (lastRegister > 0x21) {
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return DS_InvalidRegister;
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}
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tempExceptionStatus = gTRKExceptionStatus;
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gTRKExceptionStatus.exceptionDetected = FALSE;
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__TRK_set_MSR(__TRK_get_MSR() | 0x2000);
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*registersLengthPtr = 0;
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error = DS_NoError;
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for (current = firstRegister;
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(current <= lastRegister) && (error == DS_NoError);
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current++, *registersLengthPtr += sizeof(f64)) {
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if (read) {
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TRKPPCAccessFPRegister(&temp, current, read);
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error = TRKAppendBuffer1_ui64(b, temp);
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} else {
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TRKReadBuffer1_ui64(b, &temp);
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error = TRKPPCAccessFPRegister(&temp, current, read);
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}
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}
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if (gTRKExceptionStatus.exceptionDetected) {
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*registersLengthPtr = 0;
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error = DS_CWDSException;
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}
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gTRKExceptionStatus = tempExceptionStatus;
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return error;
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}
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DSError TRKTargetAccessExtended1(u32 firstRegister, u32 lastRegister,
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TRKBuffer* b, size_t* registersLengthPtr,
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BOOL read)
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{
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TRKExceptionStatus tempExceptionStatus;
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int error;
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u32* data;
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int count;
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if (lastRegister > 0x60) {
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return DS_InvalidRegister;
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}
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tempExceptionStatus = gTRKExceptionStatus;
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gTRKExceptionStatus.exceptionDetected = FALSE;
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*registersLengthPtr = 0;
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if (firstRegister <= lastRegister) {
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data = (u32*)&gTRKCPUState.Extended1 + firstRegister;
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count = lastRegister - firstRegister + 1;
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*registersLengthPtr += count * sizeof(u32);
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if (read) {
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error = TRKAppendBuffer_ui32(b, data, count);
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} else {
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if (data <= &gTRKCPUState.Extended1.TBU
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&& (data + count - 1) >= &gTRKCPUState.Extended1.TBL) {
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gTRKRestoreFlags.TBR = 1;
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}
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if (data <= &gTRKCPUState.Extended1.DEC
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&& (data + count - 1) >= &gTRKCPUState.Extended1.DEC) {
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gTRKRestoreFlags.DEC = 1;
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}
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error = TRKReadBuffer_ui32(b, data, count);
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}
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}
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if (gTRKExceptionStatus.exceptionDetected) {
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*registersLengthPtr = 0;
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error = DS_CWDSException;
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}
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gTRKExceptionStatus = tempExceptionStatus;
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return error;
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}
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DSError TRKTargetAccessExtended2(u32 firstRegister, u32 lastRegister,
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TRKBuffer* b, size_t* registerStorageSize,
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BOOL read)
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{
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TRKExceptionStatus savedException;
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u32 i;
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u32 value_buf0[1];
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u32 value_buf[2];
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DSError err;
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u32 access_func[10];
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if (lastRegister > 0x1f)
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return DS_InvalidRegister;
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/*
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** Save any existing exception status and clear the exception flag.
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** This allows detection of exceptions that occur ONLY within this
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** function.
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*/
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savedException = gTRKExceptionStatus;
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gTRKExceptionStatus.exceptionDetected = FALSE;
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TRKPPCAccessSPR(value_buf0, SPR_HID2, TRUE);
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value_buf0[0] |= 0xA0000000;
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TRKPPCAccessSPR(value_buf0, SPR_HID2, FALSE);
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value_buf0[0] = 0;
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TRKPPCAccessSPR(value_buf0, SPR_GQR0, FALSE);
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*registerStorageSize = 0;
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err = DS_NoError;
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for (i = firstRegister; (i <= lastRegister) && (err == DS_NoError); i++) {
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if (read) {
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err = TRKPPCAccessPairedSingleRegister((u64*)value_buf, i, read);
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err = TRKAppendBuffer1_ui64(b, *(u64*)value_buf);
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} else {
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err = TRKReadBuffer1_ui64(b, (u64*)value_buf);
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err = TRKPPCAccessPairedSingleRegister((u64*)value_buf, i, read);
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}
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*registerStorageSize += sizeof(u64);
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}
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if (gTRKExceptionStatus.exceptionDetected) {
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*registerStorageSize = 0;
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err = DS_CWDSException;
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}
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gTRKExceptionStatus = savedException;
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return err;
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}
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DSError TRKTargetVersions(DSVersions* versions)
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{
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versions->kernelMajor = 0;
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versions->kernelMinor = 10;
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versions->protocolMajor = 1;
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versions->protocolMinor = 10;
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return DS_NoError;
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}
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DSError TRKTargetSupportMask(u8 mask[32])
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{
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mask[0] = 0x7a;
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mask[1] = 0;
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mask[2] = 0x4f;
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mask[3] = 7;
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mask[4] = 0;
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mask[5] = 0;
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mask[6] = 0;
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mask[7] = 0;
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mask[8] = 0;
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mask[9] = 0;
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mask[10] = 0;
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mask[0xb] = 0;
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mask[0xc] = 0;
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mask[0xd] = 0;
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mask[0xe] = 0;
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mask[0xf] = 0;
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mask[0x10] = 1;
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mask[0x11] = 0;
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mask[0x12] = 3;
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mask[0x13] = 0;
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mask[0x14] = 0;
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mask[0x15] = 0;
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mask[0x16] = 0;
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mask[0x17] = 0;
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mask[0x18] = 0;
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mask[0x19] = 0;
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mask[0x1a] = 3;
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mask[0x1b] = 0;
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mask[0x1c] = 0;
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mask[0x1d] = 0;
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mask[0x1e] = 0;
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mask[0x1f] = 0x80;
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return DS_NoError;
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}
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extern BOOL gTRKBigEndian;
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|
|
DSError TRKTargetCPUType(DSCPUType* cpuType)
|
|
{
|
|
cpuType->cpuMajor = 0;
|
|
cpuType->cpuMinor = TRKTargetCPUMinorType();
|
|
cpuType->bigEndian = gTRKBigEndian;
|
|
cpuType->defaultTypeSize = 4;
|
|
cpuType->fpTypeSize = 8;
|
|
cpuType->extended1TypeSize = 4;
|
|
cpuType->extended2TypeSize = 8;
|
|
return DS_NoError;
|
|
}
|
|
|
|
asm void TRKInterruptHandler()
|
|
{
|
|
#ifdef __MWERKS__ // clang-format off
|
|
nofralloc
|
|
mtsrr0 r2
|
|
mtsrr1 r4
|
|
mfsprg r4, 3
|
|
mfcr r2
|
|
mtsprg 3, r2
|
|
lis r2, gTRKState@h
|
|
ori r2, r2, gTRKState@l
|
|
lwz r2, TRKState_PPC.MSR(r2)
|
|
ori r2, r2, 0x8002
|
|
xori r2, r2, 0x8002
|
|
sync
|
|
mtmsr r2
|
|
sync
|
|
lis r2, TRK_saved_exceptionID@h
|
|
ori r2, r2, TRK_saved_exceptionID@l
|
|
sth r3, 0(r2)
|
|
cmpwi r3, 0x500
|
|
bne L_802CF694
|
|
lis r2, gTRKCPUState@h
|
|
ori r2, r2, gTRKCPUState@l
|
|
mflr r3
|
|
stw r3, ProcessorState_PPC.transport_handler_saved_ra(r2)
|
|
bl TRKUARTInterruptHandler
|
|
lis r2, gTRKCPUState@h
|
|
ori r2, r2, gTRKCPUState@l
|
|
lwz r3, ProcessorState_PPC.transport_handler_saved_ra(r2)
|
|
mtlr r3
|
|
lis r2, gTRKState@h
|
|
ori r2, r2, gTRKState@l
|
|
lwz r2, TRKState_PPC.inputPendingPtr(r2)
|
|
lbz r2, TRKState_PPC.GPR[0](r2)
|
|
cmpwi r2, 0
|
|
beq L_802CF678
|
|
lis r2, gTRKExceptionStatus@h
|
|
ori r2, r2, gTRKExceptionStatus@l
|
|
lbz r2, TRKExceptionStatus.inTRK(r2)
|
|
cmpwi r2, 1
|
|
beq L_802CF678
|
|
lis r2, gTRKState@h
|
|
ori r2, r2, gTRKState@l
|
|
li r3, 1
|
|
stb r3, TRKState_PPC.inputActivated(r2)
|
|
b L_802CF694
|
|
L_802CF678:
|
|
lis r2, gTRKSaveState@h
|
|
ori r2, r2, gTRKSaveState@l
|
|
lwz r3, Default_PPC.CR(r2)
|
|
mtcrf 0xff, r3
|
|
lwz r3, Default_PPC.GPR[3](r2)
|
|
lwz r2, Default_PPC.GPR[2](r2)
|
|
rfi
|
|
L_802CF694:
|
|
lis r2, TRK_saved_exceptionID@h
|
|
ori r2, r2, TRK_saved_exceptionID@l
|
|
lhz r3, 0(r2)
|
|
lis r2, gTRKExceptionStatus@h
|
|
ori r2, r2, gTRKExceptionStatus@l
|
|
lbz r2, TRKExceptionStatus.inTRK(r2)
|
|
cmpwi r2, 0
|
|
bne TRKExceptionHandler
|
|
lis r2, gTRKCPUState@h
|
|
ori r2, r2, gTRKCPUState@l
|
|
stw r0, ProcessorState_PPC.Default.GPR[0](r2)
|
|
stw r1, ProcessorState_PPC.Default.GPR[1](r2)
|
|
mfsprg r0, 1
|
|
stw r0, ProcessorState_PPC.Default.GPR[2](r2)
|
|
sth r3, ProcessorState_PPC.Extended1.exceptionID(r2)
|
|
sth r3, (ProcessorState_PPC.Extended1.exceptionID + 2)(r2)
|
|
mfsprg r0, 2
|
|
stw r0, ProcessorState_PPC.Default.GPR[3](r2)
|
|
stmw r4, ProcessorState_PPC.Default.GPR[4](r2)
|
|
mfsrr0 r27
|
|
mflr r28
|
|
mfsprg r29, 3
|
|
mfctr r30
|
|
mfxer r31
|
|
stmw r27, ProcessorState_PPC.Default.PC(r2)
|
|
bl TRKSaveExtended1Block
|
|
lis r2, gTRKExceptionStatus@h
|
|
ori r2, r2, gTRKExceptionStatus@l
|
|
li r3, 1
|
|
stb r3, TRKExceptionStatus.inTRK(r2)
|
|
lis r2, gTRKState@h
|
|
ori r2, r2, gTRKState@l
|
|
lwz r0, TRKState_PPC.MSR(r2)
|
|
sync
|
|
mtmsr r0
|
|
sync
|
|
lwz r0, TRKState_PPC.LR(r2)
|
|
mtlr r0
|
|
lwz r0, TRKState_PPC.CTR(r2)
|
|
mtctr r0
|
|
lwz r0, TRKState_PPC.XER(r2)
|
|
mtxer r0
|
|
lwz r0, TRKState_PPC.DSISR(r2)
|
|
mtdsisr r0
|
|
lwz r0, TRKState_PPC.DAR(r2)
|
|
mtdar r0
|
|
lmw r3, TRKState_PPC.GPR[3](r2)
|
|
lwz r0, TRKState_PPC.GPR[0](r2)
|
|
lwz r1, TRKState_PPC.GPR[1](r2)
|
|
lwz r2, TRKState_PPC.GPR[2](r2)
|
|
b TRKPostInterruptEvent
|
|
#endif // clang-format on
|
|
}
|
|
|
|
static asm void TRKExceptionHandler(u16)
|
|
{
|
|
#ifdef __MWERKS__ // clang-format off
|
|
nofralloc
|
|
lis r2, gTRKExceptionStatus@h
|
|
ori r2, r2, gTRKExceptionStatus@l
|
|
sth r3, TRKExceptionStatus.exceptionInfo.exceptionID(r2)
|
|
mfsrr0 r3
|
|
stw r3, TRKExceptionStatus.exceptionInfo.PC(r2)
|
|
lhz r3, TRKExceptionStatus.exceptionInfo.exceptionID(r2)
|
|
cmpwi r3, 0x200
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x300
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x400
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x600
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x700
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x800
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x1000
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x1100
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x1200
|
|
beq LAB_00010ba4
|
|
cmpwi r3, 0x1300
|
|
beq LAB_00010ba4
|
|
b LAB_00010bb0
|
|
LAB_00010ba4:
|
|
mfsrr0 r3
|
|
addi r3, r3, 0x4
|
|
mtsrr0 r3
|
|
LAB_00010bb0:
|
|
lis r2, gTRKExceptionStatus@h
|
|
ori r2, r2, gTRKExceptionStatus@l
|
|
li r3, 0x1
|
|
stb r3, TRKExceptionStatus.exceptionDetected(r2)
|
|
mfsprg r3, 3
|
|
mtcrf 0xff, r3
|
|
mfsprg r2, 1
|
|
mfsprg r3, 2
|
|
rfi
|
|
#endif // clang-format on
|
|
}
|
|
|
|
void TRKPostInterruptEvent(void)
|
|
{
|
|
NubEventType eventType;
|
|
u32 inst;
|
|
TRKEvent event;
|
|
|
|
if (gTRKState.inputActivated) {
|
|
gTRKState.inputActivated = FALSE;
|
|
} else {
|
|
switch (gTRKCPUState.Extended1.exceptionID & 0xFFFF) {
|
|
case 0xd00:
|
|
case 0x700:
|
|
TRKTargetReadInstruction(&inst, gTRKCPUState.Default.PC);
|
|
|
|
if (inst == 0xfe00000) {
|
|
eventType = NUBEVENT_Support;
|
|
} else {
|
|
eventType = NUBEVENT_Breakpoint;
|
|
}
|
|
break;
|
|
default:
|
|
eventType = NUBEVENT_Exception;
|
|
break;
|
|
}
|
|
|
|
TRKConstructEvent(&event, eventType);
|
|
TRKPostEvent(&event);
|
|
}
|
|
}
|
|
|
|
asm void TRKSwapAndGo()
|
|
{
|
|
#ifdef __MWERKS__ // clang-format off
|
|
nofralloc
|
|
lis r3, gTRKState@h
|
|
ori r3, r3, gTRKState@l
|
|
stmw r0, TRKState_PPC.GPR[0](r3)
|
|
mfmsr r0
|
|
stw r0, TRKState_PPC.MSR(r3)
|
|
mflr r0
|
|
stw r0, TRKState_PPC.LR(r3)
|
|
mfctr r0
|
|
stw r0, TRKState_PPC.CTR(r3)
|
|
mfxer r0
|
|
stw r0, TRKState_PPC.XER(r3)
|
|
mfdsisr r0
|
|
stw r0, TRKState_PPC.DSISR(r3)
|
|
mfdar r0
|
|
stw r0, TRKState_PPC.DAR(r3)
|
|
li r1, -0x7ffe
|
|
nor r1, r1, r1
|
|
mfmsr r3
|
|
and r3, r3, r1
|
|
mtmsr r3
|
|
lis r2, gTRKState@h
|
|
ori r2, r2, gTRKState@l
|
|
lwz r2, TRKState_PPC.inputPendingPtr(r2)
|
|
lbz r2, TRKState_PPC.GPR[0](r2)
|
|
cmpwi r2, 0
|
|
beq L_802CF930
|
|
lis r2, gTRKState@h
|
|
ori r2, r2, gTRKState@l
|
|
li r3, 1
|
|
stb r3, TRKState_PPC.inputActivated(r2)
|
|
b TRKInterruptHandlerEnableInterrupts
|
|
L_802CF930:
|
|
lis r2, gTRKExceptionStatus@h
|
|
ori r2, r2, gTRKExceptionStatus@l
|
|
li r3, 0
|
|
stb r3, 0xc(r2)
|
|
bl TRKRestoreExtended1Block
|
|
lis r2, gTRKCPUState@h
|
|
ori r2, r2, gTRKCPUState@l
|
|
lmw r27, ProcessorState_PPC.Default.PC(r2)
|
|
mtsrr0 r27
|
|
mtlr r28
|
|
mtcrf 0xff, r29
|
|
mtctr r30
|
|
mtxer r31
|
|
lmw r3, ProcessorState_PPC.Default.GPR[3](r2)
|
|
lwz r0, ProcessorState_PPC.Default.GPR[0](r2)
|
|
lwz r1, ProcessorState_PPC.Default.GPR[1](r2)
|
|
lwz r2, ProcessorState_PPC.Default.GPR[2](r2)
|
|
rfi
|
|
#endif // clang-format on
|
|
}
|
|
|
|
asm void TRKInterruptHandlerEnableInterrupts(void)
|
|
{
|
|
#ifdef __MWERKS__ // clang-format off
|
|
nofralloc;
|
|
lis r2, gTRKState@h
|
|
ori r2, r2, gTRKState@l
|
|
lwz r0, TRKState_PPC.MSR(r2)
|
|
sync
|
|
mtmsr r0
|
|
sync
|
|
lwz r0, TRKState_PPC.LR(r2)
|
|
mtlr r0
|
|
lwz r0, TRKState_PPC.CTR(r2)
|
|
mtctr r0
|
|
lwz r0, TRKState_PPC.XER(r2)
|
|
mtxer r0
|
|
lwz r0, TRKState_PPC.DSISR(r2)
|
|
mtdsisr r0
|
|
lwz r0, TRKState_PPC.DAR(r2)
|
|
mtdar r0
|
|
lmw r3, TRKState_PPC.GPR[3](r2)
|
|
lwz r0, TRKState_PPC.GPR[0](r2)
|
|
lwz r1, TRKState_PPC.GPR[1](r2)
|
|
lwz r2, TRKState_PPC.GPR[2](r2)
|
|
b TRKPostInterruptEvent
|
|
#endif // clang-format on
|
|
}
|
|
|
|
DSError TRKTargetInterrupt(TRKEvent* event)
|
|
{
|
|
DSError error = DS_NoError;
|
|
switch (event->eventType) {
|
|
case NUBEVENT_Breakpoint:
|
|
case NUBEVENT_Exception:
|
|
if (TRKTargetCheckStep() == FALSE) {
|
|
TRKTargetSetStopped(TRUE);
|
|
error = TRKDoNotifyStopped(DSMSG_NotifyStopped);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
DSError TRKTargetAddStopInfo(TRKBuffer* buffer)
|
|
{
|
|
DSError error;
|
|
u32 instruction;
|
|
s32 i;
|
|
|
|
error = TRKAppendBuffer1_ui32(buffer, gTRKCPUState.Default.PC);
|
|
if (error == DS_NoError) {
|
|
error = TRKTargetReadInstruction(&instruction, gTRKCPUState.Default.PC);
|
|
}
|
|
if (error == DS_NoError)
|
|
error = TRKAppendBuffer1_ui32(buffer, instruction);
|
|
if (error == DS_NoError)
|
|
error = TRKAppendBuffer1_ui16(buffer, gTRKCPUState.Extended1.exceptionID);
|
|
|
|
if (error == DS_NoError) {
|
|
for (i = 0; i < 32; i++) {
|
|
error = TRKAppendBuffer1_ui32(buffer, (u16) gTRKCPUState.Default.GPR[i]);
|
|
}
|
|
for (i = 0; i < 32; i++) {
|
|
error = TRKAppendBuffer1_ui64(buffer, (u16) gTRKCPUState.Float.FPR[i]);
|
|
}
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
DSError TRKTargetAddExceptionInfo(TRKBuffer* buffer)
|
|
{
|
|
DSError error;
|
|
u32 local_10;
|
|
|
|
error = TRKAppendBuffer1_ui32(buffer, gTRKExceptionStatus.exceptionInfo.PC);
|
|
if (error == 0) {
|
|
error = TRKTargetReadInstruction(&local_10,
|
|
gTRKExceptionStatus.exceptionInfo.PC);
|
|
}
|
|
if (error == 0) {
|
|
error = TRKAppendBuffer1_ui32(buffer, local_10);
|
|
}
|
|
if (error == 0) {
|
|
error = TRKAppendBuffer1_ui16(
|
|
buffer, gTRKExceptionStatus.exceptionInfo.exceptionID);
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
static DSError TRKTargetEnableTrace(BOOL val)
|
|
{
|
|
if (val) {
|
|
gTRKCPUState.Extended1.MSR = (gTRKCPUState.Extended1.MSR | 0x400);
|
|
} else {
|
|
gTRKCPUState.Extended1.MSR = (gTRKCPUState.Extended1.MSR & ~0x400);
|
|
}
|
|
return DS_NoError;
|
|
}
|
|
|
|
static BOOL TRKTargetStepDone()
|
|
{
|
|
BOOL result = TRUE;
|
|
|
|
if (gTRKStepStatus.active
|
|
&& ((u16)gTRKCPUState.Extended1.exceptionID) == PPC_Trace) {
|
|
switch (gTRKStepStatus.type) {
|
|
case DSSTEP_IntoCount:
|
|
if (gTRKStepStatus.count > 0) {
|
|
result = FALSE;
|
|
}
|
|
break;
|
|
case DSSTEP_IntoRange:
|
|
if (gTRKCPUState.Default.PC >= gTRKStepStatus.rangeStart
|
|
&& gTRKCPUState.Default.PC <= gTRKStepStatus.rangeEnd) {
|
|
result = FALSE;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
return result;
|
|
}
|
|
|
|
static DSError TRKTargetDoStep()
|
|
{
|
|
gTRKStepStatus.active = TRUE;
|
|
TRKTargetEnableTrace(TRUE);
|
|
|
|
if (gTRKStepStatus.type == DSSTEP_IntoCount
|
|
|| gTRKStepStatus.type == DSSTEP_OverCount) {
|
|
gTRKStepStatus.count--;
|
|
}
|
|
|
|
TRKTargetSetStopped(FALSE);
|
|
return DS_NoError;
|
|
}
|
|
|
|
static BOOL TRKTargetCheckStep()
|
|
{
|
|
if (gTRKStepStatus.active) {
|
|
TRKTargetEnableTrace(FALSE);
|
|
|
|
if (TRKTargetStepDone()) {
|
|
gTRKStepStatus.active = FALSE;
|
|
} else {
|
|
TRKTargetDoStep();
|
|
}
|
|
}
|
|
|
|
return gTRKStepStatus.active;
|
|
}
|
|
|
|
DSError TRKTargetSingleStep(u32 count, BOOL stepOver)
|
|
{
|
|
DSError error = DS_NoError;
|
|
|
|
if (stepOver) {
|
|
error = DS_UnsupportedError;
|
|
} else {
|
|
gTRKStepStatus.type = DSSTEP_IntoCount;
|
|
gTRKStepStatus.count = count;
|
|
error = TRKTargetDoStep();
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
DSError TRKTargetStepOutOfRange(u32 rangeStart, u32 rangeEnd, BOOL stepOver)
|
|
{
|
|
DSError error = DS_NoError;
|
|
|
|
if (stepOver) {
|
|
// Stepping over isn't supported for PowerPC
|
|
error = DS_UnsupportedError;
|
|
} else {
|
|
gTRKStepStatus.type = DSSTEP_IntoRange;
|
|
// gTRKStepStatus.active = TRUE;
|
|
gTRKStepStatus.rangeStart = rangeStart;
|
|
gTRKStepStatus.rangeEnd = rangeEnd;
|
|
error = TRKTargetDoStep();
|
|
}
|
|
|
|
return error;
|
|
}
|
|
|
|
u32 TRKTargetGetPC() { return gTRKCPUState.Default.PC; }
|
|
|
|
DSError TRKTargetSupportRequest(void) {
|
|
DSError error;
|
|
u32 spC;
|
|
size_t* length;
|
|
MessageCommandID commandId;
|
|
TRKEvent event;
|
|
u8 ioResult;
|
|
|
|
commandId = (u8) gTRKCPUState.Default.GPR[3];
|
|
if (commandId != DSMSG_ReadFile && commandId != DSMSG_WriteFile && commandId != DSMSG_OpenFile && commandId != DSMSG_CloseFile && commandId != DSMSG_PositionFile) {
|
|
TRKConstructEvent(&event, NUBEVENT_Exception);
|
|
TRKPostEvent(&event);
|
|
return DS_NoError;
|
|
}
|
|
if (commandId == DSMSG_OpenFile) {
|
|
error = HandleOpenFileSupportRequest((char*) gTRKCPUState.Default.GPR[4], gTRKCPUState.Default.GPR[5], (u32*) gTRKCPUState.Default.GPR[6], &ioResult);
|
|
if (ioResult == DS_IONoError && error != DS_NoError) {
|
|
ioResult = DS_IOError;
|
|
}
|
|
gTRKCPUState.Default.GPR[3] = ioResult;
|
|
} else if (commandId == DSMSG_CloseFile) {
|
|
error = HandleCloseFileSupportRequest(gTRKCPUState.Default.GPR[4], &ioResult);
|
|
if (ioResult == DS_IONoError && error != DS_NoError) {
|
|
ioResult = DS_IOError;
|
|
}
|
|
gTRKCPUState.Default.GPR[3] = ioResult;
|
|
} else if (commandId == DSMSG_PositionFile) {
|
|
spC = *((u32*) gTRKCPUState.Default.GPR[5]);
|
|
error = HandlePositionFileSupportRequest(gTRKCPUState.Default.GPR[4], &spC, gTRKCPUState.Default.GPR[6], &ioResult);
|
|
if (ioResult == DS_IONoError && error != DS_NoError) {
|
|
ioResult = DS_IOError;
|
|
}
|
|
gTRKCPUState.Default.GPR[3] = ioResult;
|
|
*((u32*) gTRKCPUState.Default.GPR[5]) = spC;
|
|
} else {
|
|
length = (size_t*) gTRKCPUState.Default.GPR[5];
|
|
error = TRKSuppAccessFile((u8) gTRKCPUState.Default.GPR[4], (u8*) gTRKCPUState.Default.GPR[6], length, (DSIOResult*) &ioResult, TRUE, commandId == DSMSG_ReadFile);
|
|
if (ioResult == DS_IONoError && error != DS_NoError) {
|
|
ioResult = DS_IOError;
|
|
}
|
|
gTRKCPUState.Default.GPR[3] = ioResult;
|
|
if (commandId == DSMSG_ReadFile) {
|
|
TRK_flush_cache((void*) gTRKCPUState.Default.GPR[6], *length);
|
|
}
|
|
}
|
|
gTRKCPUState.Default.PC += 4;
|
|
return error;
|
|
}
|
|
|
|
DSError TRKTargetFlushCache(u8, void* start, void* end)
|
|
{
|
|
if (start < end) {
|
|
TRK_flush_cache(start, (u8*)end - (u8*)start);
|
|
return DS_NoError;
|
|
}
|
|
|
|
return DS_InvalidMemory;
|
|
}
|
|
|
|
BOOL TRKTargetStopped() { return gTRKState.isStopped; }
|
|
|
|
void TRKTargetSetStopped(unsigned int stopped)
|
|
{
|
|
gTRKState.isStopped = stopped;
|
|
}
|
|
|
|
u32 TRKTargetStop()
|
|
{
|
|
TRKTargetSetStopped(1);
|
|
return 0;
|
|
}
|
|
|
|
DSError TRKPPCAccessSPR(void* value, u32 spr_register_num, BOOL read)
|
|
{
|
|
/* Initialize instruction array with nop */
|
|
|
|
u32 access_func[10] = {
|
|
INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP,
|
|
INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP
|
|
};
|
|
/*
|
|
** Construct a small assembly function to perform the
|
|
** requested access and call it. The read/write function
|
|
** is in the form:
|
|
**
|
|
** read:
|
|
** mfspr r4, spr_register_num
|
|
** stw r4, 0(r3)
|
|
** blr
|
|
**
|
|
** write:
|
|
** lwz r4, 0(r3)
|
|
** mtspr spr_register_num, r4
|
|
** blr
|
|
**
|
|
*/
|
|
|
|
if (read) {
|
|
access_func[0] = INSTR_MFSPR(4, spr_register_num);
|
|
access_func[1] = (u32)INSTR_STW(4, 0, 3);
|
|
} else {
|
|
access_func[0] = (u32)INSTR_LWZ(4, 0, 3);
|
|
access_func[1] = INSTR_MTSPR(spr_register_num, 4);
|
|
}
|
|
|
|
return TRKPPCAccessSpecialReg(value, access_func, read);
|
|
}
|
|
|
|
DSError TRKPPCAccessPairedSingleRegister(void* srcDestPtr, u32 psr, BOOL read)
|
|
{
|
|
// all nop by default
|
|
u32 instructionData[] = {
|
|
INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP,
|
|
INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP
|
|
};
|
|
|
|
if (read) {
|
|
instructionData[0]
|
|
= INSTR_PSQ_ST(psr, 0, 3, 0, 0); // psq_st psr, 0(r3), 0, 0
|
|
} else {
|
|
instructionData[0]
|
|
= INSTR_PSQ_L(psr, 0, 3, 0, 0); // psq_l psr, 0(r3), 0, 0
|
|
}
|
|
|
|
return TRKPPCAccessSpecialReg(srcDestPtr, instructionData, read);
|
|
}
|
|
|
|
#pragma dont_inline on
|
|
DSError TRKPPCAccessFPRegister(void* srcDestPtr, u32 fpr, BOOL read)
|
|
{
|
|
DSError error = DS_NoError;
|
|
// all nop by default
|
|
u32 instructionData1[] = {
|
|
INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP,
|
|
INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP, INSTR_NOP
|
|
};
|
|
|
|
if (fpr < 0x20) {
|
|
if (read) {
|
|
instructionData1[0] = INSTR_STFD(fpr, 0, 3); // stfd fpr, 0(r3)
|
|
} else {
|
|
instructionData1[0] = INSTR_LFD(fpr, 0, 3); // lfd fpr, 0(r3)
|
|
}
|
|
|
|
error = TRKPPCAccessSpecialReg(srcDestPtr, instructionData1, read);
|
|
} else if (fpr == 0x20) {
|
|
*(u64*)srcDestPtr &= 0xFFFFFFFF;
|
|
} else if (fpr == 0x21) {
|
|
if (!read) {
|
|
*(u32*)srcDestPtr = *((u32*)(srcDestPtr) + 1);
|
|
}
|
|
error = TRKPPCAccessSPR(srcDestPtr, 1022, read);
|
|
if (read) {
|
|
DSFetch_u64(srcDestPtr) = DSFetch_u32(srcDestPtr) & 0xffffffffLL;
|
|
}
|
|
}
|
|
|
|
return error;
|
|
}
|
|
#pragma dont_inline reset
|
|
|
|
#define DEBUG_VECTORREG_ACCESS 0
|
|
|
|
DSError TRKPPCAccessSpecialReg(void* value, u32* access_func, BOOL read)
|
|
{
|
|
typedef void (*asm_access_type)(void*, void*);
|
|
|
|
asm_access_type asm_access;
|
|
|
|
/*
|
|
** Construct a small assembly function to perform the
|
|
** requested access and call it. The read/write function
|
|
** is in the form:
|
|
**
|
|
** <access_func>
|
|
** blr
|
|
*/
|
|
|
|
/*
|
|
** Put blr instruction at the end of access function (it should be
|
|
** a 5-instruction array w/the last one empty).
|
|
*/
|
|
|
|
access_func[9] = INSTR_BLR;
|
|
|
|
/*
|
|
** Now that the instruction array is built, get a function pointer to it.
|
|
*/
|
|
|
|
asm_access = (asm_access_type)access_func;
|
|
|
|
#if DEBUG_VECTORREG_ACCESS
|
|
|
|
__puts("\r\nasm_access: ");
|
|
__puthex8((u32)asm_access);
|
|
__puts(" access_func: ");
|
|
__puthex8((u32)access_func);
|
|
|
|
for (i = 0; i < 10; i++) {
|
|
__puts("\r\ninst[");
|
|
__puthex2(i);
|
|
__puts("]: ");
|
|
__puthex8(access_func[i]);
|
|
__puts(" ; ");
|
|
__puthex8(*((u32*)asm_access + i));
|
|
}
|
|
|
|
__puts("\r\n");
|
|
|
|
#endif
|
|
|
|
// Flush cache
|
|
TRK_flush_cache((void*)(u32)access_func, (sizeof(access_func) * 10));
|
|
(*asm_access)((u32*)value, (void*)&TRKvalue128_temp);
|
|
|
|
return DS_NoError;
|
|
}
|
|
|
|
void TRKTargetSetInputPendingPtr(void* ptr) { gTRKState.inputPendingPtr = ptr; }
|