cdb1d1fc37
* Match mtx and Padclamp.c * Match the rest of GX * Import TRK 2.6 * Import MSL headers and files * Merge some MSL headers into ours
559 lines
18 KiB
C
559 lines
18 KiB
C
#include <dolphin/PPCArch.h>
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#include <dolphin/gx.h>
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#include <dolphin/os.h>
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#include <stddef.h>
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#include <dolphin/gx/GXPriv.h>
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static struct __GXFifoObj* CPUFifo;
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static struct __GXFifoObj* GPFifo;
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static OSThread* __GXCurrentThread;
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static GXBool CPGPLinked;
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static BOOL GXOverflowSuspendInProgress;
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static GXBreakPtCallback BreakPointCB;
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static u32 __GXOverflowCount;
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void* __GXCurrentBP;
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static void __GXFifoReadEnable(void);
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static void __GXFifoReadDisable(void);
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static void __GXFifoLink(u8 arg0);
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static void __GXWriteFifoIntEnable(u8 arg0, u8 arg1);
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static void __GXWriteFifoIntReset(u8 arg0, u8 arg1);
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static void GXOverflowHandler(s16 interrupt, OSContext *context)
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{
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ASSERTLINE(0x179, !GXOverflowSuspendInProgress);
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__GXOverflowCount++;
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__GXWriteFifoIntEnable(0, 1);
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__GXWriteFifoIntReset(1, 0);
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GXOverflowSuspendInProgress = TRUE;
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OSSuspendThread(__GXCurrentThread);
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}
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static void GXUnderflowHandler(s16 interrupt, OSContext *context)
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{
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ASSERTLINE(0x1A3, GXOverflowSuspendInProgress);
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OSResumeThread(__GXCurrentThread);
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GXOverflowSuspendInProgress = FALSE;
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__GXWriteFifoIntReset(1U, 1U);
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__GXWriteFifoIntEnable(1U, 0U);
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}
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#define SOME_SET_REG_MACRO(reg, size, shift, val) \
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do { \
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(reg) = (u32)__rlwimi((u32)(reg), (val), (shift), (32 - (shift) - (size)), (31 - (shift))); \
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} while (0);
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static void GXBreakPointHandler(s16 interrupt, OSContext *context)
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{
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OSContext exceptionContext;
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gx->cpEnable = gx->cpEnable & 0xFFFFFFDF;
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__cpReg[1] = gx->cpEnable;
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if (BreakPointCB != NULL) {
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OSClearContext(&exceptionContext);
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OSSetCurrentContext(&exceptionContext);
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BreakPointCB();
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OSClearContext(&exceptionContext);
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OSSetCurrentContext(context);
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}
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}
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static void GXCPInterruptHandler(s16 interrupt, OSContext *context)
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{
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gx->cpStatus = GX_GET_CP_REG(0);
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if (GET_REG_FIELD(gx->cpEnable, 1, 3) && GET_REG_FIELD(gx->cpStatus, 1, 1)) {
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GXUnderflowHandler(interrupt, context);
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}
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if (GET_REG_FIELD(gx->cpEnable, 1, 2) && GET_REG_FIELD(gx->cpStatus, 1, 0)) {
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GXOverflowHandler(interrupt, context);
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}
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if (GET_REG_FIELD(gx->cpEnable, 1, 5) && GET_REG_FIELD(gx->cpStatus, 1, 4)) {
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GXBreakPointHandler(interrupt, context);
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}
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}
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void GXInitFifoBase(GXFifoObj *fifo, void *base, u32 size)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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ASSERTMSGLINE(0x21E, realFifo != CPUFifo, "GXInitFifoBase: fifo is attached to CPU");
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ASSERTMSGLINE(0x220, realFifo != GPFifo, "GXInitFifoBase: fifo is attached to GP");
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ASSERTMSGLINE(0x222, ((u32)base & 0x1F) == 0, "GXInitFifoBase: base must be 32B aligned");
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ASSERTMSGLINE(0x224, base != NULL, "GXInitFifoBase: base pointer is NULL");
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ASSERTMSGLINE(0x226, (size & 0x1F) == 0, "GXInitFifoBase: size must be 32B aligned");
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ASSERTMSGLINE(0x228, size >= 0x10000, "GXInitFifoBase: fifo is not large enough");
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realFifo->base = base;
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realFifo->top = (u8 *)base + size - 4;
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realFifo->size = size;
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realFifo->count = 0;
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GXInitFifoLimits(fifo, size - 0x4000, (size >> 1) & ~0x1F);
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GXInitFifoPtrs(fifo, base, base);
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}
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void GXInitFifoPtrs(GXFifoObj *fifo, void *readPtr, void *writePtr)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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BOOL enabled;
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ASSERTMSGLINE(0x250, realFifo != CPUFifo, "GXInitFifoPtrs: fifo is attached to CPU");
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ASSERTMSGLINE(0x252, realFifo != GPFifo, "GXInitFifoPtrs: fifo is attached to GP");
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ASSERTMSGLINE(0x254, ((u32)readPtr & 0x1F) == 0, "GXInitFifoPtrs: readPtr not 32B aligned");
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ASSERTMSGLINE(0x256, ((u32)writePtr & 0x1F) == 0, "GXInitFifoPtrs: writePtr not 32B aligned");
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ASSERTMSGLINE(0x259, realFifo->base <= readPtr && readPtr < realFifo->top, "GXInitFifoPtrs: readPtr not in fifo range");
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ASSERTMSGLINE(0x25C, realFifo->base <= writePtr && writePtr < realFifo->top, "GXInitFifoPtrs: writePtr not in fifo range");
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enabled = OSDisableInterrupts();
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realFifo->rdPtr = readPtr;
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realFifo->wrPtr = writePtr;
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realFifo->count = (u8 *)writePtr - (u8 *)readPtr;
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if (realFifo->count < 0) {
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realFifo->count += realFifo->size;
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}
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OSRestoreInterrupts(enabled);
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}
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void GXInitFifoLimits(GXFifoObj *fifo, u32 hiWatermark, u32 loWatermark)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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ASSERTMSGLINE(0x281, realFifo != GPFifo, "GXInitFifoLimits: fifo is attached to GP");
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ASSERTMSGLINE(0x283, (hiWatermark & 0x1F) == 0, "GXInitFifoLimits: hiWatermark not 32B aligned");
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ASSERTMSGLINE(0x285, (loWatermark & 0x1F) == 0, "GXInitFifoLimits: loWatermark not 32B aligned");
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ASSERTMSGLINE(0x287, hiWatermark < realFifo->top - realFifo->base, "GXInitFifoLimits: hiWatermark too large");
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ASSERTMSGLINE(0x289, loWatermark < hiWatermark, "GXInitFifoLimits: hiWatermark below lo watermark");
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realFifo->hiWatermark = hiWatermark;
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realFifo->loWatermark = loWatermark;
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}
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void GXSetCPUFifo(GXFifoObj *fifo)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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BOOL enabled = OSDisableInterrupts();
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CPUFifo = realFifo;
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if (CPUFifo == GPFifo)
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{
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u32 reg = 0;
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__piReg[3] = (u32)realFifo->base & 0x3FFFFFFF;
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__piReg[4] = (u32)realFifo->top & 0x3FFFFFFF;
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SET_REG_FIELD(0x294, reg, 21, 5, ((u32)realFifo->wrPtr & 0x3FFFFFFF) >> 5);
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SET_REG_FIELD(0x295, reg, 1, 26, 0);
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__piReg[5] = reg;
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CPGPLinked = GX_TRUE;
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__GXWriteFifoIntReset(1, 1);
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__GXWriteFifoIntEnable(1, 0);
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__GXFifoLink(1);
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}
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else
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{
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u32 reg;
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if (CPGPLinked)
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{
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__GXFifoLink(0);
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CPGPLinked = GX_FALSE;
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}
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__GXWriteFifoIntEnable(0, 0);
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reg = 0;
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__piReg[3] = (u32)realFifo->base & 0x3FFFFFFF;
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__piReg[4] = (u32)realFifo->top & 0x3FFFFFFF;
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SET_REG_FIELD(0x2B7, reg, 21, 5, ((u32)realFifo->wrPtr & 0x3FFFFFFF) >> 5);
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SET_REG_FIELD(0x2B8, reg, 1, 26, 0);
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__piReg[5] = reg;
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}
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__sync();
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OSRestoreInterrupts(enabled);
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}
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void GXSetGPFifo(GXFifoObj *fifo)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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BOOL enabled = OSDisableInterrupts();
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__GXFifoReadDisable();
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__GXWriteFifoIntEnable(0, 0);
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GPFifo = realFifo;
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GX_SET_CP_REG(16, (u32)realFifo->base & 0xFFFF);
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GX_SET_CP_REG(18, (u32)realFifo->top & 0xFFFF);
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GX_SET_CP_REG(24, realFifo->count & 0xFFFF);
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GX_SET_CP_REG(26, (u32)realFifo->wrPtr & 0xFFFF);
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GX_SET_CP_REG(28, (u32)realFifo->rdPtr & 0xFFFF);
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GX_SET_CP_REG(20, (u32)realFifo->hiWatermark & 0xFFFF);
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GX_SET_CP_REG(22, (u32)realFifo->loWatermark & 0xFFFF);
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GX_SET_CP_REG(17, ((u32)realFifo->base & 0x3FFFFFFF) >> 16);
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GX_SET_CP_REG(19, ((u32)realFifo->top & 0x3FFFFFFF) >> 16);
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GX_SET_CP_REG(25, realFifo->count >> 16);
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GX_SET_CP_REG(27, ((u32)realFifo->wrPtr & 0x3FFFFFFF) >> 16);
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GX_SET_CP_REG(29, ((u32)realFifo->rdPtr & 0x3FFFFFFF) >> 16);
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GX_SET_CP_REG(21, (u32)realFifo->hiWatermark >> 16);
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GX_SET_CP_REG(23, (u32)realFifo->loWatermark >> 16);
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__sync();
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if (CPUFifo == GPFifo) {
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CPGPLinked = GX_TRUE;
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__GXWriteFifoIntEnable(1, 0);
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__GXFifoLink(1);
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}
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else {
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CPGPLinked = GX_FALSE;
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__GXWriteFifoIntEnable(0, 0);
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__GXFifoLink(0);
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}
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__GXWriteFifoIntReset(1, 1);
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__GXFifoReadEnable();
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OSRestoreInterrupts(enabled);
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}
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void GXSaveCPUFifo(GXFifoObj *fifo)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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ASSERTMSGLINE(0x343, realFifo == CPUFifo, "GXSaveCPUFifo: fifo is not attached to CPU");
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__GXSaveCPUFifoAux(realFifo);
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}
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#define SOME_MACRO1(fifo) \
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do { \
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u32 temp = GX_GET_CP_REG(29) << 16; \
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temp |= GX_GET_CP_REG(28); \
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fifo->rdPtr = OSPhysicalToCached(temp); \
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} while (0)
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#define SOME_MACRO2(fifo) \
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do { \
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u32 temp = GX_GET_CP_REG(25) << 16; \
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temp |= GX_GET_CP_REG(24); \
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fifo->count = temp; \
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} while (0)
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void __GXSaveCPUFifoAux(struct __GXFifoObj *realFifo)
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{
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BOOL enabled = OSDisableInterrupts();
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GXFlush();
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realFifo->base = OSPhysicalToCached(__piReg[3]);
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realFifo->top = OSPhysicalToCached(__piReg[4]);
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realFifo->wrPtr = OSPhysicalToCached(__piReg[5] & 0xFBFFFFFF);
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if (CPGPLinked) {
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SOME_MACRO1(realFifo);
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SOME_MACRO2(realFifo);
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} else {
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realFifo->count = (u8 *)realFifo->wrPtr - (u8 *)realFifo->rdPtr;
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if (realFifo->count < 0)
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realFifo->count += realFifo->size;
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}
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OSRestoreInterrupts(enabled);
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}
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void GXSaveGPFifo(GXFifoObj *fifo)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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unsigned long cpStatus;
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unsigned char readIdle;
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unsigned long temp;
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ASSERTMSGLINE(0x38C, realFifo == GPFifo, "GXSaveGPFifo: fifo is not attached to GP");
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cpStatus = GX_GET_CP_REG(0);
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readIdle = GET_REG_FIELD(cpStatus, 1, 2);
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ASSERTMSGLINE(0x393, readIdle, "GXSaveGPFifo: GP is not idle");
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SOME_MACRO1(realFifo);
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SOME_MACRO2(realFifo);
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}
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void GXGetGPStatus(GXBool *overhi, GXBool *underlow, GXBool *readIdle, GXBool *cmdIdle, GXBool *brkpt)
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{
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gx->cpStatus = GX_GET_CP_REG(0);
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*overhi = GET_REG_FIELD(gx->cpStatus, 1, 0);
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*underlow = (int)GET_REG_FIELD(gx->cpStatus, 1, 1);
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*readIdle = (int)GET_REG_FIELD(gx->cpStatus, 1, 2);
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*cmdIdle = (int)GET_REG_FIELD(gx->cpStatus, 1, 3);
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*brkpt = (int)GET_REG_FIELD(gx->cpStatus, 1, 4);
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}
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void GXGetFifoStatus(GXFifoObj *fifo, GXBool *overhi, GXBool *underflow, u32 *fifoCount, GXBool *cpuWrite, GXBool *gpRead, GXBool *fifowrap)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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*underflow = GX_FALSE;
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*overhi = GX_FALSE;
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*fifoCount = 0;
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*fifowrap = GX_FALSE;
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if (realFifo == GPFifo) {
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SOME_MACRO1(realFifo);
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SOME_MACRO2(realFifo);
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}
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if (realFifo == CPUFifo) {
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GXFlush();
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__GXSaveCPUFifoAux(realFifo);
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*fifowrap = (int)GET_REG_FIELD(GX_GET_PI_REG(5), 1, 26);
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}
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*overhi = (realFifo->count > realFifo->hiWatermark);
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*underflow = (realFifo->count < realFifo->loWatermark);
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*fifoCount = (realFifo->count);
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*cpuWrite = (CPUFifo == realFifo);
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*gpRead = (GPFifo == realFifo);
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}
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void GXGetFifoPtrs(GXFifoObj *fifo, void **readPtr, void **writePtr)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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if (realFifo == CPUFifo) {
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realFifo->wrPtr = OSPhysicalToCached(GX_GET_PI_REG(5) & 0xFBFFFFFF);
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}
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if (realFifo == GPFifo) {
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SOME_MACRO1(realFifo);
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SOME_MACRO2(realFifo);
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}
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else {
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realFifo->count = (u8 *)realFifo->wrPtr - (u8 *)realFifo->rdPtr;
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if (realFifo->count < 0) {
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realFifo->count += realFifo->size;
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}
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}
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*readPtr = realFifo->rdPtr;
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*writePtr = realFifo->wrPtr;
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}
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void *GXGetFifoBase(const GXFifoObj *fifo)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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return realFifo->base;
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}
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u32 GXGetFifoSize(const GXFifoObj *fifo)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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return realFifo->size;
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}
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void GXGetFifoLimits(const GXFifoObj *fifo, u32 *hi, u32 *lo)
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{
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struct __GXFifoObj *realFifo = (struct __GXFifoObj *)fifo;
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*hi = realFifo->hiWatermark;
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*lo = realFifo->loWatermark;
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}
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GXBreakPtCallback GXSetBreakPtCallback(GXBreakPtCallback cb)
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{
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GXBreakPtCallback oldcb = BreakPointCB;
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BOOL enabled = OSDisableInterrupts();
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BreakPointCB = cb;
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OSRestoreInterrupts(enabled);
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return oldcb;
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}
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void *__GXCurrentBP;
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void GXEnableBreakPt(void *break_pt)
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{
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BOOL enabled = OSDisableInterrupts();
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__GXFifoReadDisable();
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GX_SET_CP_REG(30, (u32)break_pt);
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GX_SET_CP_REG(31, ((u32)break_pt >> 16) & 0x3FFF);
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SOME_SET_REG_MACRO(gx->cpEnable, 1, 1, 1);
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SOME_SET_REG_MACRO(gx->cpEnable, 1, 5, 1);
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GX_SET_CP_REG(1, gx->cpEnable);
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__GXCurrentBP = break_pt;
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__GXFifoReadEnable();
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OSRestoreInterrupts(enabled);
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}
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void GXDisableBreakPt(void)
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{
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BOOL enabled = OSDisableInterrupts();
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SOME_SET_REG_MACRO(gx->cpEnable, 1, 1, 0);
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SOME_SET_REG_MACRO(gx->cpEnable, 1, 5, 0);
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GX_SET_CP_REG(1, gx->cpEnable);
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__GXCurrentBP = NULL;
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OSRestoreInterrupts(enabled);
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}
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void __GXFifoInit(void)
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{
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__OSSetInterruptHandler(0x11, GXCPInterruptHandler);
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__OSUnmaskInterrupts(0x4000);
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__GXCurrentThread = OSGetCurrentThread();
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GXOverflowSuspendInProgress = FALSE;
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CPUFifo = NULL;
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GPFifo = NULL;
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}
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static void __GXFifoReadEnable(void)
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{
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SET_REG_FIELD(0, gx->cpEnable, 1, 0, 1);
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GX_SET_CP_REG(1, gx->cpEnable);
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}
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static void __GXFifoReadDisable(void)
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{
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SET_REG_FIELD(0, gx->cpEnable, 1, 0, 0);
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GX_SET_CP_REG(1, gx->cpEnable);
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}
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static void __GXFifoLink(u8 en)
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{
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SET_REG_FIELD(0x4DA, gx->cpEnable, 1, 4, (en != 0) ? 1 : 0);
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GX_SET_CP_REG(1, gx->cpEnable);
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}
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static void __GXWriteFifoIntEnable(u8 hiWatermarkEn, u8 loWatermarkEn)
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{
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SET_REG_FIELD(0x4F0, gx->cpEnable, 1, 2, hiWatermarkEn);
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SET_REG_FIELD(0x4F1, gx->cpEnable, 1, 3, loWatermarkEn);
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GX_SET_CP_REG(1, gx->cpEnable);
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}
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static void __GXWriteFifoIntReset(u8 hiWatermarkClr, u8 loWatermarkClr)
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|
{
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SET_REG_FIELD(0x508, gx->cpClr, 1, 0, hiWatermarkClr);
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SET_REG_FIELD(0x509, gx->cpClr, 1, 1, loWatermarkClr);
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GX_SET_CP_REG(2, gx->cpClr);
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}
|
|
|
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void __GXInsaneWatermark(void)
|
|
{
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struct __GXFifoObj *realFifo = GPFifo;
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|
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realFifo->hiWatermark = realFifo->loWatermark + 512;
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GX_SET_CP_REG(20, (realFifo->hiWatermark & 0x3FFFFFFF) & 0xFFFF);
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GX_SET_CP_REG(21, (realFifo->hiWatermark & 0x3FFFFFFF) >> 16);
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|
}
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|
|
|
void __GXCleanGPFifo(void)
|
|
{
|
|
GXFifoObj dummyFifo;
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|
GXFifoObj *gpFifo = GXGetGPFifo();
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|
GXFifoObj *cpuFifo = GXGetCPUFifo();
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|
void *base = GXGetFifoBase(gpFifo);
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|
|
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dummyFifo = *gpFifo;
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|
GXInitFifoPtrs(&dummyFifo, base, base);
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|
GXSetGPFifo(&dummyFifo);
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|
if (cpuFifo == gpFifo) {
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|
GXSetCPUFifo(&dummyFifo);
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|
}
|
|
GXInitFifoPtrs(gpFifo, base, base);
|
|
GXSetGPFifo(gpFifo);
|
|
if (cpuFifo == gpFifo) {
|
|
GXSetCPUFifo(cpuFifo);
|
|
}
|
|
}
|
|
|
|
OSThread *GXSetCurrentGXThread(void)
|
|
{
|
|
BOOL enabled;
|
|
struct OSThread *prev;
|
|
|
|
enabled = OSDisableInterrupts();
|
|
prev = __GXCurrentThread;
|
|
ASSERTMSGLINE(0x561, !GXOverflowSuspendInProgress, "GXSetCurrentGXThread: Two threads cannot generate GX commands at the same time!");
|
|
__GXCurrentThread = OSGetCurrentThread();
|
|
OSRestoreInterrupts(enabled);
|
|
return prev;
|
|
}
|
|
|
|
OSThread *GXGetCurrentGXThread(void)
|
|
{
|
|
return __GXCurrentThread;
|
|
}
|
|
|
|
GXFifoObj *GXGetCPUFifo(void)
|
|
{
|
|
return (GXFifoObj *)CPUFifo;
|
|
}
|
|
|
|
GXFifoObj *GXGetGPFifo(void)
|
|
{
|
|
return (GXFifoObj *)GPFifo;
|
|
}
|
|
|
|
u32 GXGetOverflowCount(void)
|
|
{
|
|
return __GXOverflowCount;
|
|
}
|
|
|
|
u32 GXResetOverflowCount(void)
|
|
{
|
|
u32 oldcount;
|
|
|
|
oldcount = __GXOverflowCount;
|
|
__GXOverflowCount = 0;
|
|
return oldcount;
|
|
}
|
|
|
|
// NONMATCHING
|
|
volatile void *GXRedirectWriteGatherPipe(void *ptr)
|
|
{
|
|
u32 reg = 0;
|
|
BOOL enabled = OSDisableInterrupts();
|
|
|
|
CHECK_GXBEGIN(0x5D5, "GXRedirectWriteGatherPipe");
|
|
ASSERTLINE(0x5D6, OFFSET(ptr, 32) == 0);
|
|
ASSERTLINE(0x5D8, !IsWGPipeRedirected);
|
|
|
|
GXFlush();
|
|
while (PPCMfwpar() & 1) { }
|
|
PPCMtwpar((u32)OSUncachedToPhysical((void *)GXFIFO_ADDR));
|
|
if (CPGPLinked) {
|
|
__GXFifoLink(0);
|
|
__GXWriteFifoIntEnable(0, 0);
|
|
}
|
|
CPUFifo->wrPtr = OSPhysicalToCached(GX_GET_PI_REG(5) & 0xFBFFFFFF);
|
|
GX_SET_PI_REG(3, 0);
|
|
GX_SET_PI_REG(4, 0x04000000);
|
|
SET_REG_FIELD(0x5F7, reg, 21, 5, ((u32)ptr & 0x3FFFFFFF) >> 5);
|
|
reg &= 0xFBFFFFFF;
|
|
GX_SET_PI_REG(5, reg);
|
|
PPCSync();
|
|
OSRestoreInterrupts(enabled);
|
|
return (volatile void *)GXFIFO_ADDR;
|
|
}
|
|
|
|
// NONMATCHING
|
|
void GXRestoreWriteGatherPipe(void)
|
|
{
|
|
u32 reg = 0; // r31
|
|
u32 i; // r29
|
|
BOOL enabled; // r28
|
|
|
|
ASSERTLINE(0x610, IsWGPipeRedirected);
|
|
enabled = OSDisableInterrupts();
|
|
for (i = 0; i < 31; i++) {
|
|
GXWGFifo.u8 = 0;
|
|
}
|
|
PPCSync();
|
|
while (PPCMfwpar() & 1) { }
|
|
PPCMtwpar((u32)OSUncachedToPhysical((void *)GXFIFO_ADDR));
|
|
GX_SET_PI_REG(3, (u32)CPUFifo->base & 0x3FFFFFFF);
|
|
GX_SET_PI_REG(4, (u32)CPUFifo->top & 0x3FFFFFFF);
|
|
SET_REG_FIELD(0x62A, reg, 21, 5, ((u32)CPUFifo->wrPtr & 0x3FFFFFFF) >> 5);
|
|
reg &= 0xFBFFFFFF;
|
|
GX_SET_PI_REG(5, reg);
|
|
if (CPGPLinked) {
|
|
__GXWriteFifoIntReset(1, 1);
|
|
__GXWriteFifoIntEnable(1, 0);
|
|
__GXFifoLink(1);
|
|
}
|
|
PPCSync();
|
|
OSRestoreInterrupts(enabled);
|
|
}
|