651 lines
19 KiB
C
651 lines
19 KiB
C
#ifndef _DOLPHIN_GXPRIV
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#define _DOLPHIN_GXPRIV
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#include "dolphin/gx.h"
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#include "dolphin/os.h"
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#ifndef NDEBUG
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#define ASSERTLINE(line, cond) \
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((cond) || (OSPanic(__FILE__, line, "Failed assertion " #cond), 0))
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#define ASSERTMSGLINE(line, cond, msg) \
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((cond) || (OSPanic(__FILE__, line, msg), 0))
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// This is dumb but we dont have a Metrowerks way to do variadic macros in the macro to make this done in a not scrubby way.
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#define ASSERTMSG1LINE(line, cond, msg, arg1) \
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((cond) || (OSPanic(__FILE__, line, msg, arg1), 0))
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#define ASSERTMSG2LINE(line, cond, msg, arg1, arg2) \
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((cond) || (OSPanic(__FILE__, line, msg, arg1, arg2), 0))
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#define ASSERTMSGLINEV(line, cond, ...) \
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((cond) || (OSPanic(__FILE__, line, __VA_ARGS__), 0))
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#else
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#define ASSERTLINE(line, cond) (void)0
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#define ASSERTMSGLINE(line, cond, msg) (void)0
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#define ASSERTMSG1LINE(line, cond, msg, arg1) (void)0
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#define ASSERTMSG2LINE(line, cond, msg, arg1, arg2) (void)0
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#define ASSERTMSGLINEV(line, cond, ...) (void)0
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#endif
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typedef struct GXLightObjInt {
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u32 padding[3];
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u32 color;
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float a0;
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float a1;
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float a2;
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float k0;
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float k1;
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float k2;
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float px;
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float py;
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float pz;
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float nx;
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float ny;
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float nz;
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} GXLightObjInt;
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#define XF_LIGHT_BASE 0x0600
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#define XF_LIGHT_SIZE 0x10
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#define GX_FIFO_ADDR 0xCC008000
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#define GX_WRITE_U8(v) (GXWGFifo.u8 = v)
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#define GX_WRITE_U16(us) (GXWGFifo.u16 = (u16)(us))
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#define GX_WRITE_U32(v) (GXWGFifo.u32 = v)
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#define GX_WRITE_F32(f) (GXWGFifo.f32 = (f32)(f))
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#if DEBUG
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#define VERIF_XF_REG(addr, value) \
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do { \
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s32 regAddr = (addr); \
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if (regAddr >= 0 && regAddr < 0x50) { \
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__gxVerif->xfRegs[regAddr] = (value); \
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__gxVerif->xfRegsDirty[regAddr] = 1; \
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} \
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} while (0)
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#define VERIF_XF_REG_alt(addr, value) \
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do { \
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s32 xfAddr = (addr); \
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if (xfAddr >= 0 && xfAddr < 0x50) { \
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__gxVerif->xfRegs[xfAddr] = (value); \
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__gxVerif->xfRegsDirty[xfAddr] = 1; \
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} \
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} while (0)
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#define VERIF_RAS_REG(value) (__gxVerif->rasRegs[((value) & 0xFF000000) >> 24] = value)
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#define VERIF_MTXLIGHT(addr, data) \
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do { \
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s32 xfAddr; \
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if (addr < 0x400U) { \
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__gxVerif->xfMtx[addr] = data; \
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__gxVerif->xfMtxDirty[addr] = 1; \
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} else if (addr < 0x500U) { \
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xfAddr = addr - 0x400; \
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__gxVerif->xfNrm[xfAddr] = data; \
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__gxVerif->xfNrmDirty[xfAddr] = 1; \
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} else if (addr < 0x600U) { \
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xfAddr = addr - 0x500; \
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__gxVerif->xfDMtx[xfAddr] = data; \
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__gxVerif->xfDMtxDirty[xfAddr] = 1; \
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} else if (addr < 0x680U) { \
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xfAddr = addr - 0x600; \
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__gxVerif->xfLight[xfAddr] = data; \
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__gxVerif->xfLightDirty[xfAddr] = 1; \
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} else { \
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xfAddr = addr - 0x1000; \
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if ((xfAddr >= 0) && (xfAddr < 0x50)) { \
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__gxVerif->xfRegs[xfAddr] = data; \
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__gxVerif->xfRegsDirty[xfAddr] = 1; \
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} \
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} \
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} while (0)
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#else
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#define VERIF_XF_REG(addr, value) ((void)0)
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#define VERIF_XF_REG_alt(addr, value) ((void)0)
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#define VERIF_RAS_REG(value) ((void)0)
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#endif
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#define GX_WRITE_XF_REG(addr, value) \
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do { \
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GX_WRITE_U8(0x10); \
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GX_WRITE_U32(0x1000 + (addr)); \
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GX_WRITE_U32(value); \
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VERIF_XF_REG(addr, value); \
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} while (0)
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#if DEBUG
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#define GX_WRITE_XF_REG_2(addr, value) \
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do { \
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u32 xfData = (value); &xfData; \
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GX_WRITE_U32(value); \
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VERIF_XF_REG_alt(addr, xfData); \
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} while (0)
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#define GX_WRITE_XF_REG_F(addr, value) \
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do { \
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f32 xfData = (value); \
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GX_WRITE_F32(value); \
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VERIF_XF_REG_alt(addr, *(u32 *)&xfData); \
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} while (0)
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#else
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#define GX_WRITE_XF_REG_2(addr, value) \
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do { \
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GX_WRITE_U32(value); \
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} while (0)
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#define GX_WRITE_XF_REG_F(addr, value) \
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do { \
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GX_WRITE_F32(value); \
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} while (0)
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#endif
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#define GX_WRITE_RAS_REG(value) \
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do { \
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GX_WRITE_U8(0x61); \
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GX_WRITE_U32(value); \
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VERIF_RAS_REG(value); \
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} while (0)
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#define GX_WRITE_SOME_REG2(a, b, c, addr) \
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do { \
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long regAddr; \
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GX_WRITE_U8(a); \
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GX_WRITE_U8(b); \
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GX_WRITE_U32(c); \
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regAddr = addr; \
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if (regAddr >= 0 && regAddr < 4) { \
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gx->indexBase[regAddr] = c; \
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} \
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} while (0)
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#define GX_WRITE_SOME_REG3(a, b, c, addr) \
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do { \
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long regAddr; \
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GX_WRITE_U8(a); \
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GX_WRITE_U8(b); \
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GX_WRITE_U32(c); \
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regAddr = addr; \
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if (regAddr >= 0 && regAddr < 4) { \
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gx->indexStride[regAddr] = c; \
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} \
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} while (0)
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#define GX_WRITE_SOME_REG4(a, b, c, addr) \
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do { \
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long regAddr; \
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GX_WRITE_U8(a); \
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GX_WRITE_U8(b); \
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GX_WRITE_U32(c); \
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regAddr = addr; \
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} while (0)
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#define GET_REG_FIELD(reg, size, shift) ((int)((reg) >> (shift)) & ((1 << (size)) - 1))
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#define SET_REG_FIELD(line, reg, size, shift, val) \
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do { \
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ASSERTMSGLINE(line, ((u32)(val) & ~((1 << (size)) - 1)) == 0, "GX Internal: Register field out of range"); \
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(reg) = ((u32)(reg) & ~(((1 << (size)) - 1) << (shift))) | ((u32)(val) << (shift)); \
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} while (0)
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#define GX_REG_ASSERT(c) ASSERTMSG(c, "GX Internal: Register field out of range")
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#define GX_FLAG_SET(regOrg, newFlag, regName) \
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do { \
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GX_REG_ASSERT(!((newFlag) & ~((1 << (regName##_SIZE)) - 1))); \
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(regOrg) = (((u32)(regOrg) & ~(regName##_MASK)) | \
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(((u32)(newFlag) << (regName##_SHIFT)) & (regName##_MASK))); \
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} while (0)
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#define GX_GENMODE_ID 0
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#define GX_GENMODE_REG_ID_SIZE 8
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#define GX_GENMODE_REG_ID_SHIFT 24
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#define GX_GENMODE_REG_ID_MASK 0xff000000
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#define GX_GENMODE_GET_REG_ID(genMode) \
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((((u32)(genMode)) & GX_GENMODE_REG_ID_MASK) >> GX_GENMODE_REG_ID_SHIFT)
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#define GX_BPMASK_ID 15
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#define GX_BPMASK_REG_ID_SIZE 8
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#define GX_BPMASK_REG_ID_SHIFT 24
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#define GX_BPMASK_REG_ID_MASK 0xff000000
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#define GX_LPSIZE_ID 34
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#define GX_LPSIZE_REG_ID_SIZE 8
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#define GX_LPSIZE_REG_ID_SHIFT 24
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#define GX_LPSIZE_REG_ID_MASK 0xff000000
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#define TEV_COLOR_ENV_REG_ID_SIZE 8
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#define TEV_COLOR_ENV_REG_ID_SHIFT 24
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#define TEV_COLOR_ENV_REG_ID_MASK 0xff000000
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#define TEV_ALPHA_ENV_REG_ID_SIZE 8
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#define TEV_ALPHA_ENV_REG_ID_SHIFT 24
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#define TEV_ALPHA_ENV_REG_ID_MASK 0xff000000
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#define TEV_COLOR_ENV_0_ID 0x000000c0
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#define TEV_ALPHA_ENV_0_ID 0x000000c1
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#define TEV_COLOR_ENV_1_ID 0x000000c2
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#define TEV_ALPHA_ENV_1_ID 0x000000c3
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#define TEV_COLOR_ENV_2_ID 0x000000c4
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#define TEV_ALPHA_ENV_2_ID 0x000000c5
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#define TEV_COLOR_ENV_3_ID 0x000000c6
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#define TEV_ALPHA_ENV_3_ID 0x000000c7
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#define TEV_COLOR_ENV_4_ID 0x000000c8
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#define TEV_ALPHA_ENV_4_ID 0x000000c9
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#define TEV_COLOR_ENV_5_ID 0x000000ca
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#define TEV_ALPHA_ENV_5_ID 0x000000cb
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#define TEV_COLOR_ENV_6_ID 0x000000cc
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#define TEV_ALPHA_ENV_6_ID 0x000000cd
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#define TEV_COLOR_ENV_7_ID 0x000000ce
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#define TEV_ALPHA_ENV_7_ID 0x000000cf
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#define TEV_COLOR_ENV_8_ID 0x000000d0
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#define TEV_ALPHA_ENV_8_ID 0x000000d1
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#define TEV_COLOR_ENV_9_ID 0x000000d2
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#define TEV_ALPHA_ENV_9_ID 0x000000d3
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#define TEV_COLOR_ENV_A_ID 0x000000d4
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#define TEV_ALPHA_ENV_A_ID 0x000000d5
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#define TEV_COLOR_ENV_B_ID 0x000000d6
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#define TEV_ALPHA_ENV_B_ID 0x000000d7
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#define TEV_COLOR_ENV_C_ID 0x000000d8
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#define TEV_ALPHA_ENV_C_ID 0x000000d9
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#define TEV_COLOR_ENV_D_ID 0x000000da
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#define TEV_ALPHA_ENV_D_ID 0x000000db
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#define TEV_COLOR_ENV_E_ID 0x000000dc
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#define TEV_ALPHA_ENV_E_ID 0x000000dd
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#define TEV_COLOR_ENV_F_ID 0x000000de
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#define TEV_ALPHA_ENV_F_ID 0x000000df
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#define TEV_KSEL_REG_ID_SIZE 8
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#define TEV_KSEL_REG_ID_SHIFT 24
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#define TEV_KSEL_REG_ID_MASK 0xff000000
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#define TEV_KSEL_0_ID 0x000000f6
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#define TEV_KSEL_1_ID 0x000000f7
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#define TEV_KSEL_2_ID 0x000000f8
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#define TEV_KSEL_3_ID 0x000000f9
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#define TEV_KSEL_4_ID 0x000000fa
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#define TEV_KSEL_5_ID 0x000000fb
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#define TEV_KSEL_6_ID 0x000000fc
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#define TEV_KSEL_7_ID 0x000000fd
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#define RAS_IREF_ID 39
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#define RAS_IREF_REG_ID_SIZE 8
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#define RAS_IREF_REG_ID_SHIFT 24
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#define RAS_IREF_REG_ID_MASK 0xff000000
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#define RAS_TREF0_ID 40
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#define RAS_TREF_REG_ID_SIZE 8
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#define RAS_TREF_REG_ID_SHIFT 24
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#define RAS_TREF_REG_ID_MASK 0xff000000
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#define SU_TS0_REG_ID_SIZE 8
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#define SU_TS0_REG_ID_SHIFT 24
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#define SU_TS0_REG_ID_MASK 0xff000000
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#define SU_TS1_REG_ID_SIZE 8
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#define SU_TS1_REG_ID_SHIFT 24
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#define SU_TS1_REG_ID_MASK 0xff000000
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#define SU_SCIS0_ID 0x00000020
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#define SU_SCIS1_ID 0x00000021
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#define SU_SCIS0_REG_ID_SIZE 8
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#define SU_SCIS0_REG_ID_SHIFT 24
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#define SU_SCIS0_REG_ID_MASK 0xff000000
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#define SU_SCIS1_REG_ID_SIZE 8
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#define SU_SCIS1_REG_ID_SHIFT 24
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#define SU_SCIS1_REG_ID_MASK 0xff000000
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#define SU_SSIZE0_ID 0x00000030
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#define SU_TSIZE0_ID 0x00000031
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#define SU_SSIZE1_ID 0x00000032
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#define SU_TSIZE1_ID 0x00000033
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#define SU_SSIZE2_ID 0x00000034
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#define SU_TSIZE2_ID 0x00000035
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#define SU_SSIZE3_ID 0x00000036
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#define SU_TSIZE3_ID 0x00000037
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#define SU_SSIZE4_ID 0x00000038
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#define SU_TSIZE4_ID 0x00000039
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#define SU_SSIZE5_ID 0x0000003a
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#define SU_TSIZE5_ID 0x0000003b
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#define SU_SSIZE6_ID 0x0000003c
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#define SU_TSIZE6_ID 0x0000003d
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#define SU_SSIZE7_ID 0x0000003e
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#define SU_TSIZE7_ID 0x0000003f
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#define GX_ZMODE_ID 64
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#define GX_ZMODE_REG_ID_SIZE 8
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#define GX_ZMODE_REG_ID_SHIFT 24
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#define GX_ZMODE_REG_ID_MASK 0xff000000
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#define GX_CMODE0_ID 65
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#define GX_CMODE0_REG_ID_SIZE 8
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#define GX_CMODE0_REG_ID_SHIFT 24
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#define GX_CMODE0_REG_ID_MASK 0xff000000
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#define GX_CMODE1_ID 66
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#define GX_CMODE1_REG_ID_SIZE 8
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#define GX_CMODE1_REG_ID_SHIFT 24
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#define GX_CMODE1_REG_ID_MASK 0xff000000
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#define PE_CONTROL_ID 67
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#define PE_CONTROL_REG_ID_SIZE 8
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#define PE_CONTROL_REG_ID_SHIFT 24
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#define PE_CONTROL_REG_ID_MASK 0xff000000
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#define PE_COPY_CMD_GAMMA_SIZE 2
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#define PE_COPY_CMD_GAMMA_SHIFT 7
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#define PE_COPY_CMD_GAMMA_MASK 0x00000180
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#define GEN_MODE_REG_ID_SIZE 8
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#define GEN_MODE_REG_ID_SHIFT 24
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#define GEN_MODE_REG_ID_MASK 0xff000000
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#define GX_OPCODE_INDEX_SIZE 3
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#define GX_OPCODE_INDEX_SHIFT 0
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#define GX_OPCODE_INDEX_MASK 0x00000007
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#define GX_OPCODE_CMD_SHIFT 3
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#define GX_OPCODE(index, cmd) \
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((((u32)(index)) << GX_OPCODE_INDEX_SHIFT) | (((u32)(cmd)) << GX_OPCODE_CMD_SHIFT))
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#ifdef _DEBUG
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#define GX_WRITE_RA_REG(reg) \
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{ \
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GX_WRITE_U8(GX_OPCODE(1, 12)); \
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GX_WRITE_U32((reg)); \
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__gxVerif->rasRegs[GX_GENMODE_GET_REG_ID(reg)] = reg; \
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}
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#else
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#define GX_WRITE_RA_REG(reg) \
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{ \
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GX_WRITE_U8(GX_OPCODE(1, 12)); \
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GX_WRITE_U32((reg)); \
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}
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#endif
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#define CP_STREAM_REG_INDEX_SIZE 4
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#define CP_STREAM_REG_INDEX_SHIFT 0
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#define CP_STREAM_REG_INDEX_MASK 0x0000000f
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#define CP_STREAM_REG_ADDR_SIZE 4
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#define CP_STREAM_REG_ADDR_SHIFT 4
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#define CP_STREAM_REG_ADDR_MASK 0x000000f0
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#define CP_STREAM_REG(index, addr) \
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((((unsigned long)(index)) << CP_STREAM_REG_INDEX_SHIFT) | \
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(((unsigned long)(addr)) << CP_STREAM_REG_ADDR_SHIFT))
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#ifdef _DEBUG
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#define GX_WRITE_CP_STRM_REG(addr, vtxfmt, data) \
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{ \
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s32 regAddr; \
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GX_WRITE_U8(GX_OPCODE(0, 1)); \
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GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
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GX_WRITE_U32((data)); \
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regAddr = (vtxfmt)-GX_POS_MTX_ARRAY + GX_VA_POS; \
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if ((addr) == 10) { \
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if (regAddr >= 0 && regAddr < 4) \
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gx->indexBase[regAddr] = (data); \
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} else if ((addr) == 11) { \
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if (regAddr >= 0 && regAddr < 4) \
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gx->indexStride[regAddr] = (data); \
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} \
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}
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#else
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#define GX_WRITE_CP_STRM_REG(addr, vtxfmt, data) \
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{ \
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GX_WRITE_U8(GX_OPCODE(0, 1)); \
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GX_WRITE_U8(CP_STREAM_REG((vtxfmt), (addr))); \
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GX_WRITE_U32((data)); \
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}
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#endif
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#define PE_REFRESH_REG_ID_SIZE 8
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#define PE_REFRESH_REG_ID_SHIFT 24
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#define PE_REFRESH_REG_ID_MASK 0xff000000
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#define PE_REFRESH_INTERVAL_SHIFT 0
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#define PE_REFRESH_ENABLE_SHIFT 9
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#define PE_REFRESH_TOTAL_SIZE 32
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#define PE_REFRESH(interval, enable, rid) \
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((((u32)(interval)) << PE_REFRESH_INTERVAL_SHIFT) | \
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(((u32)(enable)) << PE_REFRESH_ENABLE_SHIFT) | (((u32)(rid)) << PE_REFRESH_REG_ID_SHIFT))
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#define TX_REFRESH_REG_ID_SIZE 8
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#define TX_REFRESH_REG_ID_SHIFT 24
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#define TX_REFRESH_REG_ID_MASK 0xff000000
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#define TX_REFRESH_INTERVAL_SHIFT 0
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#define TX_REFRESH_ENABLE_SHIFT 10
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#define TX_REFRESH_TOTAL_SIZE 32
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#define TX_REFRESH(interval, enable, rid) \
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((((u32)(interval)) << TX_REFRESH_INTERVAL_SHIFT) | \
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(((u32)(enable)) << TX_REFRESH_ENABLE_SHIFT) | (((u32)(rid)) << TX_REFRESH_REG_ID_SHIFT))
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#define GX_VAT_REG_A_UNK_SIZE 1
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#define GX_VAT_REG_A_UNK_SHIFT 30
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#define GX_VAT_REG_A_UNK_MASK 0x40000000
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#define GX_VAT_REG_B_UNK_SIZE 1
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#define GX_VAT_REG_B_UNK_SHIFT 31
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#define GX_VAT_REG_B_UNK_MASK 0x80000000
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#define GX_GET_MEM_REG(offset) (*(volatile u16*)((volatile u16*)(__memReg) + (offset)))
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#define GX_GET_CP_REG(offset) (*(volatile u16*)((volatile u16*)(__cpReg) + (offset)))
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#define GX_GET_PE_REG(offset) (*(volatile u16*)((volatile u16*)(__peReg) + (offset)))
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#define GX_GET_PI_REG(offset) (*(volatile u32*)((volatile u32*)(__piReg) + (offset)))
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#define GX_SET_MEM_REG(offset, val) (*(volatile u16*)((volatile u16*)(__memReg) + (offset)) = val)
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#define GX_SET_CP_REG(offset, val) (*(volatile u16*)((volatile u16*)(__cpReg) + (offset)) = val)
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#define GX_SET_PE_REG(offset, val) (*(volatile u16*)((volatile u16*)(__peReg) + (offset)) = val)
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#define GX_SET_PI_REG(offset, val) (*(volatile u32*)((volatile u32*)(__piReg) + (offset)) = val)
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#define CHECK_GXBEGIN(line, name) ASSERTMSGLINE(line, !__GXinBegin, "'" name "' is not allowed between GXBegin/GXEnd")
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/* GXAttr.c */
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void __GXSetVCD(void);
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void __GXSetVAT(void);
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/* GXBump.c */
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void __GXUpdateBPMask(void);
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void __GXFlushTextureState(void);
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/* GXFifo.c */
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// GXFifoObj private data
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struct __GXFifoObj {
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u8 *base;
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u8 *top;
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u32 size;
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u32 hiWatermark;
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u32 loWatermark;
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void *rdPtr;
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void *wrPtr;
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s32 count;
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u8 bind_cpu;
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u8 bind_gp;
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};
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void __GXSaveCPUFifoAux(struct __GXFifoObj *realFifo);
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void __GXFifoInit(void);
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void __GXInsaneWatermark(void);
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void __GXCleanGPFifo(void);
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/* GXGeometry.c */
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void __GXSetDirtyState(void);
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void __GXSendFlushPrim(void);
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void __GXSetGenMode(void);
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/* GXInit.c */
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void __GXInitGX();
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void __GXInitRevisionBits(void);
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typedef struct __GXData_struct {
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u16 vNumNot;
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u16 bpSentNot;
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u16 vNum;
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u16 vLim;
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u32 cpEnable;
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u32 cpStatus;
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u32 cpClr;
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u32 vcdLo;
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u32 vcdHi;
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u32 vatA[8];
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u32 vatB[8];
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u32 vatC[8];
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u32 lpSize;
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u32 matIdxA;
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u32 matIdxB;
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u32 indexBase[4];
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u32 indexStride[4];
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u32 ambColor[2];
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u32 matColor[2];
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u32 suTs0[8];
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u32 suTs1[8];
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u32 suScis0;
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u32 suScis1;
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u32 tref[8];
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u32 iref;
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u32 bpMask;
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u32 IndTexScale0;
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u32 IndTexScale1;
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u32 tevc[16];
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|
u32 teva[16];
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|
u32 tevKsel[8];
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|
u32 cmode0;
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|
u32 cmode1;
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|
u32 zmode;
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|
u32 peCtrl;
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|
u32 cpDispSrc;
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|
u32 cpDispSize;
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|
u32 cpDispStride;
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|
u32 cpDisp;
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|
u32 cpTexSrc;
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|
u32 cpTexSize;
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|
u32 cpTexStride;
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|
u32 cpTex;
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|
GXBool cpTexZ;
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u32 genMode;
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GXTexRegion TexRegions[8];
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GXTexRegion TexRegionsCI[4];
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u32 nextTexRgn;
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|
u32 nextTexRgnCI;
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|
GXTlutRegion TlutRegions[20];
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|
GXTexRegion* (*texRegionCallback)(GXTexObj*, GXTexMapID);
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|
GXTlutRegion* (*tlutRegionCallback)(u32);
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|
GXAttrType nrmType;
|
|
GXBool hasNrms;
|
|
GXBool hasBiNrms;
|
|
u32 projType;
|
|
f32 projMtx[6];
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|
f32 vpLeft;
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|
f32 vpTop;
|
|
f32 vpWd;
|
|
f32 vpHt;
|
|
f32 vpNearz;
|
|
f32 vpFarz;
|
|
u8 fgRange;
|
|
f32 fgSideX;
|
|
u32 tImage0[8];
|
|
u32 tMode0[8];
|
|
u32 texmapId[16];
|
|
u32 tcsManEnab;
|
|
u32 tevTcEnab;
|
|
GXPerf0 perf0;
|
|
GXPerf1 perf1;
|
|
u32 perfSel;
|
|
GXBool inDispList;
|
|
GXBool dlSaveContext;
|
|
u8 dirtyVAT;
|
|
u32 dirtyState;
|
|
} GXData;
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|
|
|
extern GXData* gx;
|
|
extern u16 *__memReg;
|
|
extern u16 *__peReg;
|
|
extern u16 *__cpReg;
|
|
extern u32 *__piReg;
|
|
// #define gx __GXData
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|
|
/* GXMisc.c */
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|
|
|
void __GXBypass(u32 reg);
|
|
u16 __GXReadPEReg(u32 reg);
|
|
void __GXPEInit(void);
|
|
void __GXAbort();
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|
|
/* GXPerf.c */
|
|
void __GXSetBWDials(u16 cpDial, u16 tcDial, u16 peDial, u16 cpuRdDial, u16 cpuWrDial);
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|
|
|
static inline u32 __GXReadCPCounterU32(u32 regAddrL, u32 regAddrH) {
|
|
u32 ctrH0;
|
|
u32 ctrH1;
|
|
u32 ctrL;
|
|
|
|
ctrH0 = GX_GET_CP_REG(regAddrH);
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|
|
|
do {
|
|
ctrH1 = ctrH0;
|
|
ctrL = GX_GET_CP_REG(regAddrL);
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|
ctrH0 = GX_GET_CP_REG(regAddrH);
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|
} while (ctrH0 != ctrH1);
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|
|
|
return (ctrH0 << 0x10) | ctrL;
|
|
}
|
|
|
|
static inline u32 __GXReadMEMCounterU32(u32 regAddrL, u32 regAddrH) {
|
|
u32 ctrH0;
|
|
u32 ctrH1;
|
|
u32 ctrL;
|
|
|
|
ctrH0 = GX_GET_MEM_REG(regAddrH);
|
|
|
|
do {
|
|
ctrH1 = ctrH0;
|
|
ctrL = GX_GET_MEM_REG(regAddrL);
|
|
ctrH0 = GX_GET_MEM_REG(regAddrH);
|
|
} while (ctrH0 != ctrH1);
|
|
|
|
return (ctrH0 << 0x10) | ctrL;
|
|
}
|
|
|
|
static inline u32 __GXReadPECounterU32(u32 regAddrL, u32 regAddrH) {
|
|
u32 ctrH0;
|
|
u32 ctrH1;
|
|
u32 ctrL;
|
|
|
|
ctrH0 = GX_GET_PE_REG(regAddrH);
|
|
|
|
do {
|
|
ctrH1 = ctrH0;
|
|
ctrL = GX_GET_PE_REG(regAddrL);
|
|
ctrH0 = GX_GET_PE_REG(regAddrH);
|
|
} while (ctrH0 != ctrH1);
|
|
|
|
return (ctrH0 << 0x10) | ctrL;
|
|
}
|
|
|
|
/* GXSave.c */
|
|
|
|
void __GXShadowDispList(void *list, u32 nbytes);
|
|
void __GXShadowIndexState(u32 idx_reg, u32 reg_data);
|
|
void __GXPrintShadowState(void);
|
|
|
|
/* GXStubs.c */
|
|
|
|
void __GXSetRange(float nearz, float fgSideX);
|
|
|
|
/* GXTexture.c */
|
|
|
|
void __GetImageTileCount(GXTexFmt fmt, u16 wd, u16 ht, u32 *rowTiles, u32 *colTiles, u32 *cmpTiles);
|
|
void __GXSetSUTexRegs(void);
|
|
void __GXGetSUTexSize(GXTexCoordID coord, u16 *width, u16 *height);
|
|
void __GXSetTmemConfig(u32 config);
|
|
|
|
/* GXTransform.c */
|
|
|
|
void __GXSetMatrixIndex(GXAttr matIdxAttr);
|
|
|
|
#endif // _DOLPHIN_GXPRIV
|