* Match mtx and Padclamp.c * Match the rest of GX * Import TRK 2.6 * Import MSL headers and files * Merge some MSL headers into ours
190 lines
4 KiB
C
190 lines
4 KiB
C
#ifndef PPC_GENERIC_TARGIMPL_H
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#define PPC_GENERIC_TARGIMPL_H
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#include "TRK_MINNOW_DOLPHIN/MetroTRK/Portable/nubevent.h"
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#include "stddef.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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void TRKTargetSetInputPendingPtr(void* ptr);
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void TRKSwapAndGo();
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void TRKTargetSetStopped(unsigned int);
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DSError TRKTargetInterrupt(TRKEvent*);
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DSError TRKTargetSupportRequest();
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void TRKDestructEvent(TRKEvent*);
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DSError TRKTargetFlushCache(u8, void* start, void* end);
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BOOL TRKTargetStopped(void);
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DSError TRKTargetAddStopInfo(TRKBuffer* b);
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DSError TRKTargetAddExceptionInfo(TRKBuffer* b);
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DSError TRKTargetAccessARAM(u32 p1, u32 p2, u32* p3, BOOL read);
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DSError TRKTargetAccessMemory(void* data, u32 start, size_t* length,
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MemoryAccessOptions accessOptions, BOOL read);
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DSError TRKTargetAccessDefault(u32 firstRegister, u32 lastRegister,
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TRKBuffer* b, size_t* registersLengthPtr,
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BOOL read);
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DSError TRKTargetAccessFP(u32 firstRegister, u32 lastRegister, TRKBuffer* b,
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size_t* registersLengthPtr, BOOL read);
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DSError TRKTargetAccessExtended1(u32 firstRegister, u32 lastRegister,
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TRKBuffer* b, size_t* registersLengthPtr,
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BOOL read);
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DSError TRKTargetAccessExtended2(u32 firstRegister, u32 lastRegister,
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TRKBuffer* b, size_t* registerStorageSize,
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BOOL read);
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u32 TRKTargetGetPC();
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DSError TRKTargetSingleStep(u32 count, BOOL stepOver);
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DSError TRKTargetStepOutOfRange(u32 rangeStart, u32 rangeEnd, BOOL stepOver);
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u32 TRKTargetStop();
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void TRKInterruptHandler();
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void TRKPostInterruptEvent(void);
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typedef struct DSVersions {
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u8 kernelMajor;
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u8 kernelMinor;
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u8 protocolMajor;
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u8 protocolMinor;
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} DSVersions;
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DSError TRKTargetVersions(DSVersions* versions);
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DSError TRKTargetSupportMask(u8 mask[32]);
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typedef struct DSCPUType {
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u8 cpuMajor;
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u8 cpuMinor;
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u8 bigEndian;
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u8 defaultTypeSize;
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u8 fpTypeSize;
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u8 extended1TypeSize;
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u8 extended2TypeSize;
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} DSCPUType;
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DSError TRKTargetCPUType(DSCPUType* cpuType);
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typedef struct Default_PPC {
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u32 GPR[32];
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u32 PC;
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u32 LR;
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u32 CR;
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u32 CTR;
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u32 XER;
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} Default_PPC;
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typedef struct Float_PPC {
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u64 FPR[32];
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u64 FPSCR;
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u64 FPECR;
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} Float_PPC;
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typedef struct Extended1_PPC_6xx_7xx {
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u32 SR[16];
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u32 TBL;
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u32 TBU;
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u32 HID0;
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u32 HID1;
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u32 MSR;
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u32 PVR;
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u32 IBAT0U;
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u32 IBAT0L;
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u32 IBAT1U;
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u32 IBAT1L;
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u32 IBAT2U;
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u32 IBAT2L;
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u32 IBAT3U;
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u32 IBAT3L;
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u32 DBAT0U;
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u32 DBAT0L;
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u32 DBAT1U;
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u32 DBAT1L;
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u32 DBAT2U;
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u32 DBAT2L;
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u32 DBAT3U;
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u32 DBAT3L;
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u32 DMISS;
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u32 DCMP;
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u32 HASH1;
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u32 HASH2;
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u32 IMISS;
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u32 ICMP;
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u32 RPA;
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u32 SDR1;
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u32 DAR;
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u32 DSISR;
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u32 SPRG0;
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u32 SPRG1;
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u32 SPRG2;
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u32 SPRG3;
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u32 DEC;
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u32 IABR;
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u32 EAR;
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u32 DABR;
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u32 PMC1;
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u32 PMC2;
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u32 PMC3;
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u32 PMC4;
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u32 SIA;
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u32 MMCR0;
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u32 MMCR1;
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u32 THRM1;
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u32 THRM2;
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u32 THRM3;
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u32 ICTC;
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u32 L2CR;
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u32 UMMCR2;
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u32 UBAMR;
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u32 UMMCR0;
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u32 UPMC1;
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u32 UPMC2;
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u32 USIA;
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u32 UMMCR1;
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u32 UPMC3;
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u32 UPMC4;
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u32 USDA;
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u32 MMCR2;
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u32 BAMR;
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u32 SDA;
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u32 MSSCR0;
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u32 MSSCR1;
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u32 PIR;
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u32 exceptionID;
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u32 GQR[8];
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u32 HID_G;
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u32 WPAR;
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u32 DMA_U;
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u32 DMA_L;
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} Extended1_PPC_6xx_7xx;
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typedef struct Extended2_PPC_6xx_7xx {
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u32 PSR[32][2];
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} Extended2_PPC_6xx_7xx;
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typedef struct ProcessorState_PPC_6xx_7xx {
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Default_PPC Default;
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Float_PPC Float;
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Extended1_PPC_6xx_7xx Extended1;
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Extended2_PPC_6xx_7xx Extended2;
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u32 transport_handler_saved_ra;
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} ProcessorState_PPC_6xx_7xx;
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typedef ProcessorState_PPC_6xx_7xx ProcessorState_PPC;
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extern ProcessorState_PPC gTRKCPUState;
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typedef struct TRKState {
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u32 gpr[32]; // _00
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u32 lr; // _80
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u32 ctr; // _84
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u32 xer; // _88
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u32 msr; // _8C
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u32 dar; // _90
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u32 dsisr; // _94
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BOOL isStopped; // _98
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BOOL inputActivated; // _9C
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void* inputPendingPtr; // _A0
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} TRKState;
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extern TRKState gTRKState;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PPC_GENERIC_TARGIMPL_H */
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